Van der Waals interface between high-$\kappa$ dielectrics and 2D semiconductors

Abstract

Atomically thin two-dimensional (2D) semiconductors are attractive channel materials for next-generation field-effect transistors (FETs). The high-performance 2D electronics requires high-quality integration of high-$\kappa$ dielectrics, which however remains a significant challenge. In this mini-review, we provide a brief introduction on recent progress in the van der Waals (vdW) integration of high-$\kappa$ dielectrics onto 2D semiconductors. We first highlight the importance of high-$\kappa$ dielectric integration for 2D FETs. Next, we summarize the recent breakthroughs in the various vdW integrations of high-$\kappa$ dielectrics with 2D semiconductors, along with their interfaces’ properties. Additionally, we examine the quasi-vdW integration of conventional high-$\kappa$ dielectrics onto 2D semiconductors. Finally, we discuss the challenges and potential future research directions in this field.

Graphical abstract

Keywords

two-dimensional semiconductor / high-$\kappa$ dielectrics / van der Waals interface

1 Introduction

Silicon-based electronics form the backbone of modern society’s technological infrastructure, which have been widely used in many aspects ranging from digital computing, automotive and transportation to health care. In the past few decades, Moore’s law and Dennard’s law pave the way for the transistor industry to improve the performance of devices by downscaling, which takes us to the 3-nm-node era in 2022 (Fig.1). However, after Si dominating market for over decades, it hits a bottleneck for further miniaturizing due to pronounced short-channel effects, difficulties in the deposition of ultra-flat Si film at atomic scale, and the significantly reduced carrier mobility [1−3].

Fig.1 Trends in transistor miniaturization over time. The main technology nodes of transistor are shown with time evolution. Four geometries of transistors are depicted with size scaling. The inset shows representative semiconductor−insulator interfaces.

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Several key techniques have been used in industry for continuing scaling Si-based devices, as illustrated in Fig.1, such as the introduction of strain-Si channel in 90-nm node, the use of high-$\kappa$ dielectrics and metal gate (HKMG) into 45-nm node, the Fin structure used in 22-nm node, and the EUV technology in 7-nm node. Topology optimization is one of the most efficient ways to scaling (Fig.1), but the approaching physical limits also force us to re-evaluate the interfacial compositions as well [4−6]. For the semiconductor part, strained-Si, strained-SiGe, SiGe, high-mobility Ge and III−V are considered as alternatives to control the unaffordable high-power consumption, low switching speed and high leakage current [7−13]. However, a solution better than present SiGe is needed to fix the large parasitic capacitance, instability of high-aspect-ratio Fins, difficulties in device epitaxy under 10-nm physical gate length. With the intrinsic atomic thicknesses and atomically flat surfaces, 2D semiconductor materials are one of the best candidates to sub-1-nm node and beyond [14−20]. Among them, transitional metal dichalcogenides (TMD) with prominent electronic properties have been identified as the most promising 2D semiconductors, especially the 2D molybdenum disulfide (MoS₂) since first monolayer TMD-FET was reported in 2011 [19, 21−25].

On the other hand, the inevitable use of high-$\kappa$ dielectrics helps to improve the gate control and electrostatics, to reduce short-channel effect, to lower operating voltage and to suppress remote phonon scattering. Although it is efficient and evidenced by the 45-nm process, directly integrating the high-$\kappa$ dielectrics like commonly used HfO₂ on 2D semiconductors remains challenging. That is mainly due to: (i) 2D semiconductors, unlike traditional bulk ones, lack dangling bonds at their surfaces. However, surface dangling bonds at the substrate are needed as nucleation centers for high-quality integration; (ii) When the high-$\kappa$ dielectrics with dangling bonds interface with the dangling-bond-free 2D semiconductors, high density of interfacial states always occur. The high interface state density is detrimental to the electronic device performance. In a word, building an ideal interface of high-$\kappa$ dielectrics on 2D semiconductors is recently a leading scheme for the development of high-performance 2D FETs [14, 15]. Some of the important criteria for device design are summarized in Tab.1.

Tab.1 The main figures of merit in FETs.

Figure of merit	Unit	Reference
Equivalent oxide thickness (EOT)	unit	1.00 [14]
Subthreshold swing (SS)	mV/dec	82 (HP), 75 (HD) [14]
Interface state density (Dit)	cm−2·eV−1	~1.0×1010 (Si/SiO2) [26]
Field-effect mobility	cm2·V−1·s−1	125 [14]
On/off ratio	unit	8.74×104 (HP), 6.44×106 (HD) [14]
Band alignment	eV	CBO > 1 eV, VBO > 1 eV [27]
Gate length	nm	16 (HP), 18 (HD) [14]
Leakage current	A/cm2	1 at ~1 V [27]
Hysteresis	mV/(MV/cm)	0.8 (SOI) [28]
Transconductance	μS/μm	1605 [14]
Saturation voltage	V	0.092 (HP), 0.104 (HD) [14]
Spacer $\kappa$ value	unit	3.2 [14]

Extensive efforts have been made to improve the integration of high-$\kappa$ dielectrics onto 2D semiconductors [29−37]. Early attempts have mainly focused on activation of 2D semiconductor surfaces to increase the number of nucleation sites for the deposition of high-$\kappa$ dielectrics [36−52]. Consequently, interface engineering strategies have also been proposed, in which buffer layers or seeding layers have been used in between high-$\kappa$ dielectrics and 2D semiconductors [37−43]. While these methods could improve the deposition quality of high-$\kappa$ dielectrics, they inevitably lead to damage to the delicate 2D structures, thus the overall device performance may not be improved. Recently, vdW integration has been developed for the high-performance integration of high-$\kappa$ dielectrics onto 2D semiconductors [35, 53−88]. The vdW integration started from the use of the layered 2D insulator such as hexagonal boron nitride (h-BN), which can naturally result in ideal interface with layered 2D semiconductors with minimized interface state density [89−93]. Consequently, we have seen the development of various other vdW interfaces formed by vdW integrating higher-$\kappa$ dielectrics onto 2D semiconductors, some of which not only show high-performance interface properties, but also demonstrate the direct integration capability [35, 64, 75−88, 94−100]. Thus, forming vdW interfaces has shown great potential for advanced 2D electronics. While we are aware that various excellent reviews have been made [35, 101−113], a mini-review remains desired, specifically for the vdW integration of high-$\kappa$ dielectrics on 2D semiconductors, due to the rapid development of this filed.

In this regard, we present a mini-review of recent process of vdW interfaces between high-$\kappa$ dielectrics and 2D semiconductors. We first introduce the experiment methods for vdW integration of high-$\kappa$ dielectrics on 2D semiconductors. Then, we highlight recent important advancements of the vdW and quasi-vdW integrations of high-$\kappa$ dielectrics. Finally, we briefly discuss the challenges, limitation and opportunities of vdW integration of high-$\kappa$ dielectrics for 2D electronics.

2 vdW integration methods

The vdW interaction consists of various dipole−dipole like interaction within materials or at the interface of heterostructures, the strength of which is several-order weaker than that of covalent bonds or ionic bonds [114]. The formation of vdW interface between high-$\kappa$ dielectrics and 2D semiconductors is highly desired as it can bring minimized damage to the 2D semiconductors. Therefore, various methods have been developed for the vdW integration of high-$\kappa$ dielectrics onto 2D semiconductors, which include top-down transfer-based integration and bottom-up direct growth as detailed below.

The top-down methods have been prevailing in years as they circumvent the possible direct damage or inconsistent fabrication conditions of each interface side [115−122]. Naturally, the hallmark of the top-down methods is the prefabricated samples, which then will be transferred onto 2D semiconductors. The most used transfer techniques consist of two main steps: detaching and stacking. Depending on whether a dry or wet environment is employed, different approaches can be devised, as illustrated in Fig.2(b). Originally, dry detaching, or mechanical exfoliation, opens the path for detaching 2D materials. Later, wet detaching becomes popular because chemical etching of growth substrates like SiO₂ enables the preparation of floating “free-standing” 2D layered materials by solution. Subsequently, the development of a modification to replace the etchant with water has been developed to remove etchant contamination, also known as “water-assisted transfer”. From the physical perspective, detaching and stacking are the processes by using the different adhesion stress between the stamp materials and the substrates. Detaching is the process where the adhesion between the 2D material and the stamp is stronger than the interlayer forces within the 2D material. In constrast, the stacking process operates in the opposite way. As a result, by leveraging disparities in solubility, hydrophilic and hydrophobic properties, viscosity variations at different temperatures, and differences in interlayer forces, one can utilize the transfer technique to obtain high-quality vdW interfaces.

Fig.2 Schematic of integration methods for vdW interfaces. (a) A typical vdW interface formed by multilayer h-BN and monolayer MoS2. (b) Top-down transfer methods. (c, d) Bottom-up methods. (e) Ink-jet method diagram.

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For bottom-up methods, the dielectric thin films can be directly synthesized on the top of 2D semiconductors. They avoid the transfer processes, thus are highly desired for large-scale integration and compatible with current semiconductor technologies. Conventional deposition methods such as sputtering or atomic layer deposition (ALD) require high-density of nucleation sites for the high-quality deposition of high-$\kappa$ dielectric films [123−126]. To improve the deposition of high-$\kappa$ dielectrics, nucleation sites are required to be introduced into inert 2D semiconductor surfaces, which however leads to damage to 2D structures and thus deteriorates their electronic properties. To mitigate these issues, various improvements have been made to either the deposition process or the choice of materials, as illustrated in Fig.2(c) and (d). The main idea in Fig.2(c) is to enable the direct growth of high-$\kappa$ dielectrics on the 2D semiconductors or on the auxiliary buffer layer. The direct growth requires a strict selection of materials to make sure that the vdW interaction can dominate [110, 114, 127, 128]. Compared to conventional buffer layer materials, new buffer layers are made of atomically sharp surfaces, which can not only facilitate the deposition of high-$\kappa$ dielectrics, but also minimize the damage to 2D channels [76, 88, 129−131]. More recently, low-temperature evaporation has been used to deposit novel high-$\kappa$ dielectric materials such as inorganic molecule crystals (IMCs) onto 2D semiconductors directly. The low-temperature evaporation process ensures the reduced damage to 2D lattice structures, and more importantly the resulting interface is vdW-like due to dangling-bond-free surface of IMCs [76]. Consequent study shows that the IMCs can also serve as both seeding and buffer layers to further deposit conventional high-$\kappa$ dielectric HfO₂, which further improves the device performance [88].

Another effective way to realize high-performance integration of high-$\kappa$ dielectrics into 2D semiconductors is through the functionalization of deposited intermediate structures, as illustrated in Fig.2(d). One of the common situations is to form vdW-type overlayer on the 2D semiconductors first, and then the overlayer will be converted into dielectric materials through the functional treatment such as oxidation. Practical systems contain but not limit to the HfX₂/HfO₂ [79, 83, 85, 86, 96, 132], Bi₂SeO₂/Bi₂SeO₅ [64, 75] and ZrX₂/ZrO₂ [95−98] interface. In addition, printing methods have been developed as a combination of bottom-up and top-down methods, such as ink-jet printing [see in Fig.2(e)] and liquid metal printing [77, 78, 80−82, 84, 94, 100], where the high-quality interfaces can also be realized.

3 vdW interfaces between high-κ dielectrics and 2D semiconductors

As discussed above, recent developments on the vdW integration of high-$\kappa$ dielectrics have resulted in much-improved device performance of 2D electronics. In this section, we summarize recent advancements in the vdW and quasi-vdW interfaces between high-$\kappa$ dielectrics and 2D semiconductors, in which interfaces involving two naturally layered 2D structures are considered as the prototypical vdW interfaces, while those formed by non-layered high-$\kappa$ dielectrics on 2D semiconductors are categorized as quasi-vdW interfaces.

3.1 vdW interfaces using top-down method

The vdW interfaces between layered 2D dielectrics and layered 2D semiconductors are commonly using top-down method, in which the pre-fabricated 2D dielectrics are transferred onto 2D semiconductors [53−63]. An example of top-down vdW integration is the use of h-BN as the dielectric and MoS₂ as the channel material [61] [see Fig.3(a)]. Owing to the stability and dangling-bond-free h-BN, the resulting devices exhibit excellent interfacial properties. Specifically, the device as shown in Fig.3(b) achieves an ultra-low interface density of ~5.2×10⁹ cm⁻²·eV⁻¹ and hysteresis as low as 0.15% of the sweeping range of bias. Such a low interface state density indicates the high interface quality. Further study has suggested that the interface properties can be improved by post-thermal annealing, as shown in Fig.3(c) and (d). Concurrently, a high on/off ratio of 10⁸ and low subthreshold swing (SS) values ranging from 63 to 69 mV/dec have been realized in h-BN/MoS₂ based devices at an operating voltage of 1 V. However, the challenges to h-BN-based MOSFET have been widely discussed. Compared to other high-$\kappa$ dielectrics like HfO₂ or SiO₂, the main drawback of h-BN is its low dielectric constant (~3.5), consequently higher leakage current under same thickness. Besides, it remains challenging to realize high-quality and large-scale growth of layered h-BN films [62].

Fig.3 Typical vdW interfaces prepared by top-down method. (a) Schematic of double-gate transistor. (b‒d) Optical image, transfer curve and comparison of hysteresis of h-BN/MoS2 device. Reproduced with permission from Ref. [61]. (e) The statistics of traditional and novel dielectric materials regarding static dielectric constant and band gap. (f) The temperature-dependent FET mobility of MoS2 on Bi2SiO5 and on SiO2. (g) Transfer curve of Bi2SiO5/MoS2 varying thickness of Bi2SiO5. Reproduced with permission from Ref. [63]. (h) Structure of LaOBr structures from high-throughput screening. Reproduced with permission from Ref. [60]. (i) Transfer curve of LaOBr/MoS2 FET. Reproduced with permission from Ref. [59].

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Consequently, various gate dielectrics with high dielectric constant have been integrated into 2D MoS₂ electronics to form vdW interface using the top-down method, as shown in Fig.3(e). Among them, a high carrier mobility (549.3 cm²·V⁻¹·s⁻¹ at 5 K) has been achieved in Bi₂Si₂O₅/MoS₂ [63], which is about 15 times higher than SiO₂ counterpart, as shown in Fig.3(f). Due to its high dielectric constant (>30), Bi₂Si₂O₅/MoS₂ based device shows a low EOT down to 1.3 nm when thickness of Bi₂Si₂O₅ is decreased to 10.1 nm, as shown in Fig.3(g). The promising device performances (SS < 70 mV/dec and hysteresis ~ 3 mV) suggest the high-performance interface of Bi₂Si₂O₅/MoS₂. However, relatively small band gap and large unit cell thickness may limit the performance in further scaling or other power transistor applications, meanwhile the large-scale synthesis and uniform growth of Bi₂Si₂O₅ thin films also deserve further studies.

In addition, high-throughput first-principal calculation has been employed to accelerate the prediction of high-performance layered 2D high-$\kappa$ dielectrics in experiments [57, 59, 60]. For example, using large-scale first-principles calculations, LaOBr has been identified as one of the most promising dielectrics screened from 457 layered materials for its proper electronic gap, high dielectric constant and low leakage current density [see Fig.3(h)] [60]. This prediction has been verified by consequent experiment, in which LaOBr thin film has been synthesized and transferred onto MoS₂ [59]. Furthermore, the associated transfer characteristics in Fig.3(i) show that LaOBr/MoS₂ device exhibits decent mobility of 32 cm²·V⁻¹·s⁻¹, low SS of 85 mV/dec, low interface state density of 1×10¹² cm⁻²·eV⁻¹ and high on/off ratio of 10⁸. These promising results confirm the contribution of high-throughput calculation to accelerate the discovery of high-performance high-$\kappa$ dielectrics for advanced 2D electronics.

3.2 Quasi-vdW interfaces using top-down method

Recently, the high-performance interface between high-$\kappa$ dielectrics and 2D semiconductors have been further exploited, enabling a vdW-type integration of those non-layered materials as the high-$\kappa$ dielectrics using the top-down method, noted as quasi-vdW interfaces. Compared to vdW interfaces, their advantage lies in the availability of a wider range of high-$\kappa$ materials, thereby significantly expanding the possible combinations of 2D semiconductors/high-$\kappa$ dielectrics interfaces.

Early quasi-vdW interface has been realized by transferring F-terminated CaF₂(111) onto MoS₂ [71], as illustrated in Fig.4(a). High-$\kappa$ dielectrics CaF₂(111) ($\kappa$~8.43) is intriguing for its naturally saturated surface, which leads to a dangling-bond free surface, in contrast with its (001) surface with dangling bonds. Thus, a high quality quasi-vdW interface can be formed, as observed in the high-resolution TEM image [Fig.4(b)], in which the thickness of the CaF₂ sample can be thinned to 2 nm. The on/off ratio of CaF₂/MoS₂ device is high to 10⁷, and its leakage current is low to 10⁻⁷ μA. As shown in Fig.4(c), the sub-1-nm EOT interface can be realized using CaF₂ as the gate dielectric, with excellent electrical stability, small hysteresis window, and high breakdown field.

Fig.4 Quasi-vdW interfaces prepared by top-down method. (a‒c) SEM image and normalized transfer curve of CaF2/MoS2 interface. Reproduced with permission from Ref. [71]. (d–g) STEM image, optical image and corresponding ID‒VG characterization of two separate research of STO/MoS2 system. Reproduced with permission from Refs. [66, 73]. (h) Main steps of fabricating quasi-vdW interface assisted by 2D surface. (i, j) AFM height measurement and double-sweep transfer curve of a wafer-scale transferred sample Al2O3 and a top-gated MoS2 FET made from wafer-scale Al2O3/MoS2. Reproduced with permission from Ref. [74].

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Gate dielectrics with higher dielectric constant such as Ta₂O₅ and perovskite oxide SrTiO₃ (STO) have also been employed to achieve quasi-vdW interface with 2D semiconductor MoS₂ [66, 73]. Especially, STO is a highly desired high-$\kappa$ dielectric material for 2D semiconductors, due to its ultra-high dielectric constant (~300). Recently, high-performance quasi-vdW interface has been realized by transferring pre-fabricated STO thin film on 2D MoS₂, as shown in STEM images and EDS mapping in Fig.4(d) and (e), respectively. The STO/MoS₂ based top-gate devices can reach an attractive electrical performance with SS of 66 mV/dec, on/off ratio of 10⁸, off-state current of 1×10⁻¹³ A, and negligible hysteresis, as shown in Fig.4(f). Furthermore, a short-channel device with channel length down to 25−55 nm has been demonstrated in STO/MoS₂, as shown in Fig.4(g). Similarly, high- $\kappa$ dielectric Ta₂O₅ ($\kappa$~15.5) has also been employ to form high-performance quasi-vdW interface with MoS₂, with high mobility of 60 cm²·V⁻¹·s⁻¹ and a SS near the Boltzmann’s limit [69].

Besides, traditional high-$\kappa$ oxides such as Al₂O₃ and HfO₂ have also been transferred on MoS₂ as the gate dielectrics. In this process, an atomically sharp sacrificial layer is used for a wafer-scale transfer, as illustrated in Fig.4(h) [65, 67, 70, 72]. Using graphene and WSe₂ as the sacrificial layer, it is shown that the direct-ALD sample is vdW-type. In Fig.4(i), a flat and wafer-scale Al₂O₃ has been fabricated, assisted by sacrificial PVA (polyvinyl alcohol) [74]. The high-$\kappa$ film was then transferred onto MoS₂ for 2D device. As shown in Fig.4(j), the MoS₂ device using the transferred HfO₂ as the gate dielectric shows low SS (68 mV/dec) and operation voltage (0.5 V), high on/off ratio of 10⁷, and small hysteresis window (~10 meV). Besides, the device performance of high-$\kappa$/MoS₂ can be further improved by inserting buffer layers such as h-BN in between high-$\kappa$ dielectrics and MoS₂, where the dangling bond effect from the dielectrics can be reduced [92, 133−135].

3.3 vdW interfaces by bottom-up methods

The top-down methods discussed above can lead to high-performance integration of high- $\kappa$ dielectrics in 2D electronics.

However, the process is dependent on the transfer technique, which not only increases the integration complexity, but also presents a grand challenge to large-scale practical applications. In this context, the bottom-up methods that are capable of directly depositing high-$\kappa$ dielectrics onto 2D semiconductors are highly desirable. Previously, direct deposition relied strongly on the high-energy deposition process, leading to damage to 2D semiconductors. Recently, various progresses have been made in this method, which can result in high-performance interface and improved device properties, as elaborated below.

One of the ideal cases is the Bi₂SeO₅/Bi₂O₂Se interface. Bi₂O₂Se is layered 2D semiconductor with a band gap of 1.09 eV, as shown in Fig.5(a) and (b). It can be directly converted to insulating phase Bi₂SeO₅ (band gap ~3.90 eV and dielectric constant ~16.5 [68]) using a UV-assisted intercalation, as illustrated in Fig.5(d). By carefully controlling the oxidation process, vdW interface can be formed between Bi₂SeO₅ and Bi₂O₂Se, as shown in Fig.5(c) [64, 75]. This interface exhibits large band offsets, where both conduction and valence band offsets exceed 1 eV, as suggested by first-principles calculations. Therefore, the vdW Bi₂SeO₅/Bi₂O₂Se interface is expected with promising device performance. As Fig.5(e) shows, the Bi₂SeO₅/Bi₂O₂Se device with ultra-thin Bi₂SeO₅ (EOT < 0.5 nm) as the gate dielectric shows outstanding transfer characteristics, such as gate leakage below 0.015 A/cm², low SS of 65 mV/dec, high mobility of 10² cm²·V⁻¹·s⁻¹, on/off ratio of 4×10⁵ and small hysteresis window of 20 mV. Further study shows that Bi₂SeO₅/Bi₂O₂Se can be used to construct inverter circuits [see Fig.5(d)] with large voltage gain. With these promising interface properties of Bi₂SeO₅/Bi₂O₂Se, their practical applications hinge on the large scale and high-quality growth of 2D semiconductor Bi₂O₂Se.

Fig.5 The vdW interfaces prepared by bottom-up method. Reproduced with permission from Refs. [68, 75]. (a) Structure information of Bi2SeO5 and Bi2O2Se. (b) Band alignment between Bi2SeO5 and Bi2O2Se. (c) STEM image of Bi2SeO5/Bi2O2Se. (d) Mechanism of unzip Bi2SeO2 by UV oxidation. (e) Transfer curve of a top-dated Bi2SeO5/Bi2O2Se FET.

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3.4 Quasi-vdW interfaces by bottom-up methods

Inorganic molecule crystals (IMCs) are emerging high-$\kappa$ dielectrics that can form quasi-vdW interface with 2D semiconductors using the bottom-up method. IMCs consist of molecule clusters bound by weak vdW interaction. This unique structural feature endows IMCs dangling-bond-free surface, and more importantly, they could be directly deposited on 2D semiconductors at low temperature. For instance, as shown in Fig.6(a), IMC Sb₂O₃ was grown on a substrate before being integrated onto MoS₂ using thermal evaporation at a relatively low temperature [76]. The resulting high-performance vdW interface and minimized damage to MoS₂ can be seen from the outstanding device performance, in which high carrier mobility (145 cm²·V⁻¹·s⁻¹), large on/off ratio (>10⁸), and low SS (64 mV/dec) have been achieved. However, due to the relatively small band gap (~3.9 eV) and loose structure, its band offsets with monolayer MoS₂ might not be large enough and the leakage current is notably increased when the thickness of Sb₂O₃ is decreased.

Fig.6 Quasi-vdW interfaces prepared by bottom-up method. (a) Structure information of inorganic molecular crystal Sb2O3. Reproduced with permission from Ref. [76]. (b‒d) Schematic diagram of interface, cross-sectional STEM image, SS statistics and short-channel transfer curve based on HfO2/MoS2 transistor with Sb2O3 buffer layer. Reproduced with permission from Ref. [88]. (e‒h) Schematic diagram, STEM image and performance curve of PTCDA-assisted HfO2/MoS2. Reproduced with permission from Ref. [35]. (i) Schematic diagram of HfO2/HfS2 transistor. Reproduced with permission from Ref. [83]. (j) TEM image of HfO2/HfS2 by ozone plasma. Reproduced with permission from Ref. [79]. (k) Liquid metal printing processes. Reproduced with permission from Ref. [84]. (l‒m) MoS2 ink preparation and fabrication process of an all-ink-jet printing HfO2/MoS2 FET. Reproduced with permission from Ref. [77].

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To address the above issues, further improvement has been made by directly evaporating a thin layer of Sb₂O₃ on MoS₂ [88], followed by ALD growth of HfO₂ [see Fig.6(b) and (c)]. The thin Sb₂O₃ layer serves as both seeding and buffer layers, in which its hydrophilic surface enables the ALD deposition of HfO₂ thin film, and it also reduces the dangling bond effect of HfO₂ on the channel MoS₂. Therefore, improved electrical performance has been demonstrated in HfO₂/Sb₂O₃/MoS₂ based devices, as shown in Fig.6(d). Similar efforts include the use of molecular crystal 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) as the buffer/seeding layer. As shown in Fig.6(e), an atomically thin PTCDA layer (~0.3 nm) was deposited on MoS₂ using chemical vapor deposition (CVD), and then HfO₂ was grown on PTCDA [35]. A high-performance interface can be formed, as shown in Fig.6(f), which is evidenced by the promising device performance [see Fig.6(g) and (h)]. While this method looks quite promising to achieve high-performance integration of high-$\kappa$ dielectrics for 2D electronics, further efforts are needed to explore the large-scale, uniform, and low temperature growth of the buffer/seeding layers with minimum impact on the 2D semiconductors.

Interface engineering has also been employed to try to achieve quasi-vdW interface between conventional high-$\kappa$ oxides and 2D semiconductors [79, 83, 85−87, 99]. For example, for the layered 2D HfS₂, oxidation has been carried out to oxidize the top layers of HfS₂ and form HfO₂ using ozone plasma. Photo-oxidation [Fig.6(i)] [83] and revised ozone treatment [Fig.6(j)] [79] have been used to convert HfS₂/MoS₂ into HfO₂/MoS₂, respectively. The resulting quasi-vdW interface of HfO₂/HfS₂ can be seen from the HETEM image in Fig.6(j). The corresponding devices show improved electric performance such as high on/off ratio, small SS (63 mV/dec), and negligible hysteresis window. The main challenge of this interface engineering is on the control of the treatment process, which should realize large-scale high-quality high-$\kappa$ oxides while not damaging the 2D semiconductors. Besides, first-principles calculations have revealed that interface hydrogenation can selectively passivate the surface dangling bonds of HfO₂ while not affecting 2D semiconductors such as MoS₂, leading to high-performance interface. However, this theoretic prediction awaits further experimental verification [36].

Moreover, to meet the high-yield, low-cost, large-area production, ink-jet printing methods are employed into laboratory and industry more and more frequently [77, 78, 80−82, 84]. Diverse vdW materials are able to be assembled by different electronic 2D materials inks. Owing to the versatility of liquid-phase exfoliation, various 2D vdW high-$\kappa$/semiconductors devices can be fabricated by ink-jet printing, thus making it a promising way to manufactory. For instance, MoS₂-based ink-jet printing utilize pre-fabricated MoS₂ nanosheets by means in Fig.6(l) [77] or electrochemical exfoliation [81]. In an entirely ink-jet printing case shown in Fig.6(m), the quasi-vdW surfaces created by the ink-jet printed devices have capability in large-scale fabrication with high mobility of 10 cm²·V⁻¹·s⁻¹ high on/off ratio over 10⁵. Similarly, the method shown in Fig.6(k) necessitates the selection of an appropriate liquid metal system to form high-performance oxide interfaces at ambient conditions [84]. From the lower Fig.6(k) we can clearly identify a vdW-gap between WS₂ and Ga₂O₃. However, the high leakage current of 2.4×10⁻⁴ A/cm², and trapping state density of 4.8×10¹² cm⁻²·eV⁻¹ in this device indicates that further improvement is needed for this kind of system. Besides, the accurate control of layer-by-layer deposition remains the issue to take advantages of 2D layered materials, since the agglomeration, low uniformity and uncovered regions always hinder the transport properties.

4 Perspectives and conclusions

In summary, this mini-review briefly introduces recent advances in the vdW-integrations of high-$\kappa$ dielectrics onto 2D semiconductors, in which both top-down (transfer) and bottom-up (direct growth) methods, along with their representative examples, have been discussed.

Significant progresses have been made in both integration methods for the high-performance high-$\kappa$ dielectrics/2D semiconductors interfaces. As shown in Fig.7, we have selected the on/off ratio and SS together to evaluate various results. The performance variation reflects the interface quality, and device configurations such as the thickness of the dielectrics and the semiconductors and the channel length. An interface that excels in both SS value and switching ratio must be sufficiently thin and efficient. Thinner dielectrics provide better gate control, as indicated by SS, but suffer from large leakage current as indicated by the on/off ratio, and vice versa. According to this trade-off, some further research of high-$\kappa$ dielectric integration on 2D semiconductors could be inferred to further improve the device performance.

Fig.7 Scattering diagram of various high-$\kappa$/2D interfaces, with the x-axis representing the on/off ratio and the y-axis representing the subthreshold swing (SS). Red circles indicate interfaces made by top-down methods, while blue circles represent those made by bottom-up methods. The size of each circle corresponds to the $\kappa$ value, with larger circles indicating higher $\kappa$ values. The three crosses at the top of the diagram indicate systems with excessively high SS values. Each interface is labeled with brief information.

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Through all these studies, the overall performances and qualities of high-$\kappa$ dielectrics/2D semiconductors achieved through top-down methods surpass those obtained via bottom-up approaches, and wafer-scale samples typically exhibit inferior performance compared to experiment-scale ones. In comparison to h-BN, several high-$\kappa$ dielectrics using the top-down method have already surpassed its interface performance, as illustrated in Fig.7, with the best devices approaching both the Boltzmann limit and a high switching ratio of 10⁸. These include SrTiO₃, Bi₂SiO₅, and Bi₂SeO₅. In most large-scale scenarios, unacceptably high SS and low switching ratios are still observed. While large-scale transfer techniques can address challenges associated with uniformity and interface quality [72, 74, 136−141], more efforts are needed to address the issues such as high process complexity and low process uniformity. For the bottom-up approaches, they offer advantages such as better scalability and greater compatibility with existing semiconductor fabrication processes. However, they still have significant room for the improvement of interface quality.

To improve the integration performance, the research on the below topics is necessary: (i) To explore the high-$\kappa$ materials with high dielectric constant and large band offsets with promising 2D semiconductors such as MoS₂. These high-$\kappa$ dielectric candidates should be able to be directly deposited on the 2D semiconductor with high-quality using a low-energy and low-temperature deposition process to minimize the growth impact to the 2D semiconductors. Such exploration requires the search on the vast material space, thus a synergistic effort of high-throughput first-principles calculations, machine learning technologies, and experiments is needed to accelerate the development process; (ii) To explore better molecular crystal-based buffer, seeding layers or sacrificial layers. Currently, molecular crystals such as Sb₂O₃ or PTCDA can be directly grown on 2D semiconductor MoS₂ at low temperature, without bringing noticeable damage to MoS₂, thus serving as promising buffer/seeding layers for the ALD growth of high-performance high-$\kappa$ oxides such as HfO₂. Molecular crystals with better dielectric performance and compatible with consequent ALD growth are highly desired to further improve the device performance and scaling capability; (iii) To have an improved understanding of the interface between buffer layers/2D semiconductors and also the interface between buffer layers and high-$\kappa$ materials. The interface properties such as defect properties, band alignments, leakage current, and interface stability are crucial to improve the integration performance, thus both experimental and computational efforts are required to elucidate these effects.

Optimistically speaking, with the extensive efforts on the exploration of high-$\kappa$ dielectrics for 2D semiconductors, high-performance interface could be achieved to meet the practical requirements of advanced 2D electronics. Along with other breakthroughs such as the growth of 2D semiconductors, metal contact, doping, and device optimization, it is promising to realize high-performance 2D electronics.

References

[1] R. K. Ratnesh, , A. Goel, , G. Kaushik, , H. Garg, , Chandan , , M. Singh, , and and B. Prasad, Advancement and challenges in MOSFET scaling, Mater. Sci. Semicond. Process. 134, 106002 (2021)

[2] U. König, Challenges for a Si/Ge heterodevice technology, Microelectron. Eng. 23(1−4), 3 (1994)

[3] R. Sharma and A. K. Rana, Strained Si. Opportunities and challenges in nanoscale MOSFET, in: 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS), 2015, pp 475–480

[4] G. Bae, D. I. Bae, M. Kang, S. M. Hwang, S. S. Kim, B. Seo, T. Y. Kwon, T. J. Lee, C. Moon, Y. M. Choi, K. Oikawa, S. Masuoka, K. Y. Chun, S. H. Park, H. J. Shin, J. C. Kim, K. K. Bhuwalka, D. H. Kim, W. J. Kim, J. Yoo, H. Y. Jeon, M. S. Yang, S. J. Chung, D. Kim, B. H. Ham, K. J. Park, W. D. Kim, S. H. Park, G. Song, Y. H. Kim, M. S. Kang, K. H. Hwang, C. H. Park, J. H. Lee, D. W. Kim, S. M. Jung, and H. K. Kang, 3 nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications, in: 2018 IEEE International Electron Devices Meeting (IEDM) (2018), pp 28.7.1–28.7.4

[5] U. Nanda, , K. Bhol, , and and B. Jena, Journey of MOSFET from planar to gate all around: A review, Recent Pat. Nanotechnol. 16(4), 326 (2022)

[6] B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, L. Witters, S. Biesemans, and T. Hoffman, The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET, in: 2009 International Symposium on VLSI Technology, Systems, and Applications, 2009, pp 80–81

[7] S. Verdonckt-Vandebroek, , E. F. Crabbe, , B. S. Meyerson, , D. L. Harame, , P. J. Restle, , J. M. C. Stork, , A. C. Megdanis, , C. L. Stanis, , A. A. Bright, , G. M. W. Kroesen, , and and A. C. Warren, High-mobility modulation-doped SiGe-channel p-MOSFETs, IEEE Electron Device Lett. 12, 447 (1991)

[8] M. Yang, , R. Q. Wu, , W. S. Deng, , L. Shen, , Z. D. Sha, , Y. Q. Cai, , Y. P. Feng, , and and S. J. Wang, Electronic structures of β-Si₃N₄ (0001)/Si (111) interfaces: Perfect bonding and dangling bond effects, J. Appl. Phys. 105(2), 024108 (2009)

[9] D. P. Brunco, , B. De Jaeger, , G. Eneman, , J. Mitard, , G. Hellings, , A. Satta, , V. Terzieva, , L. Souriau, , F. E. Leys, , G. Pourtois, , M. Houssa, , G. Winderickx, , E. Vrancken, , S. Sioncke, , K. Opsomer, , G. Nicholas, , M. Caymax, , A. Stesmans, , J. Van Steenbergen, , P. W. Mertens, , M. Meuris, , and and M. M. Heyns, Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance, J. Electrochem. Soc. 155(7), H552 (2008)

[10] K. Saraswat, , C. O. Chui, , T. Krishnamohan, , D. Kim, , A. Nayfeh, , and and A. Pethe, High performance germanium MOSFETs, Mater. Sci. Eng. B 135(3), 242 (2006)

[11] S. Chattopadhyay, , L. D. Driscoll, , K. S. K. Kwa, , S. H. Olsen, , and and A. G. O’Neill, Strained Si MOSFETs on relaxed SiGe platforms: Performance and challenges, Solid-State Electron. 48(8), 1407 (2004)

[12] M. L. Lee, , E. A. Fitzgerald, , M. T. Bulsara, , M. T. Currie, , and A. Lochtefeld, , and Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors, J. Appl. Phys. 97(1), 011101 (2005)

[13] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, Strained silicon MOSFET technology, in: Digest, International Electron Devices Meeting, 2002, pp 23–26

[14] IRDS^TM 2022: More than Moore − IEEE IRDS^TM, URL: irds.ieee.org/editions/2022/irds%E2%84%A2-2022-more-than-moore

[15] IRDS^TM 2023: Beyond CMOS and Emerging Materials Integration − IEEE IRDS^TM, URL: irds.ieee.org/editions/2023/20-roadmap-2023-edition/126-irds%E2%84%A2-2023-beyond-cmos-and-emerging-materials-integration

[16] L. W. Wong, , K. Yang, , W. Han, , X. Zheng, , H. Y. Wong, , C. S. Tsang, , C. S. Lee, , S. P. Lau, , T. H. Ly, , M. Yang, , and and J. Zhao, Deciphering the ultra-high plasticity in metal monochalcogenides, Nat. Mater. 23(2), 196 (2024)

[17] H. K. Ng, , D. Xiang, , A. Suwardi, , G. Hu, , K. Yang, , Y. Zhao, , T. Liu, , Z. Cao, , H. Liu, , S. Li, , J. Cao, , Q. Zhu, , Z. Dong, , C. K. I. Tan, , D. Chi, , C. W. Qiu, , K. Hippalgaonkar, , G. Eda, , M. Yang, , and and J. Wu, Improving carrier mobility in two-dimensional semiconductors with rippled materials, Nat. Electron. 5(8), 489 (2022)

[18] M. Yang, , J. W. Chai, , M. Callsen, , J. Zhou, , T. Yang, , T. T. Song, , J. S. Pan, , D. Z. Chi, , Y. P. Feng, , and and S. J. Wang, Interfacial interaction between HfO₂ and MoS₂: From thin films to monolayer, J. Phys. Chem. C 120(18), 9804 (2016)

[19] J. Chai, , S. Tong, , C. Li, , C. Manzano, , B. Li, , Y. Liu, , M. Lin, , L. Wong, , J. Cheng, , J. Wu, , A. Lau, , Q. Xie, , S. J. Pennycook, , H. Medina, , M. Yang, , S. Wang, , and and D. Chi, MoS₂/polymer heterostructures enabling stable resistive switching and multistate randomness, Adv. Mater. 32(42), 2002704 (2020)

[20] W. Han, , X. Zheng, , K. Yang, , C. S. Tsang, , F. Zheng, , L. W. Wong, , K. H. Lai, , T. Yang, , Q. Wei, , M. Li, , W. F. Io, , F. Guo, , Y. Cai, , N. Wang, , J. Hao, , S. P. Lau, , C. S. Lee, , T. H. Ly, , M. Yang, , and and J. Zhao, Phase-controllable large-area two-dimensional In₂Se₃ and ferroelectric heterophase junction, Nat. Nanotechnol. 18(1), 55 (2023)

[21] X. Tong, , E. Ashalley, , F. Lin, , H. Li, , and and Z. M. Wang, Advances in MoS₂-based field effect transistors (FETs), Nano-Micro Lett. 7(3), 203 (2015)

[22] I. Shlyakhov, J. Chai, M. Yang, S. Wang, V. V. Afanas’ev, M. Houssa, and A. Stesmans, Energy band alignment of a monolayer MoS₂ with SiO₂ and Al₂O₃ insulators from internal photoemission, Phys. Status Solidi. A 216(8), 1800616 (2019) (a)

[23] W. Bao, , X. Cai, , D. Kim, , K. Sridhara, , and and M. S. Fuhrer, High mobility ambipolar MoS₂ field-effect transistors: Substrate and dielectric effects, Appl. Phys. Lett. 102(4), 042104 (2013)

[24] A. Rai, , H. C. P. Movva, , A. Roy, , D. Taneja, , S. Chowdhury, , and and S. K. Banerjee, Progress in contact, doping and mobility engineering of MoS₂: An atomically thin 2D semiconductor, Crystals (Basel) 8(8), 316 (2018)

[25] B. Radisavljevic, , A. Radenovic, , J. Brivio, , V. Giacometti, , and and A. Kis, Single-layer MoS₂ transistors, Nat. Nanotechnol. 6(3), 147 (2011)

[26] T. Boutchacha, , G. Ghibaudo, , G. Guégan, , and and T. Skotnicki, Low frequency noise characterization of 0.18 μm Si CMOS transistors, Microelectron. Reliab. 37(10−11), 1599 (1997)

[27] J. Robertson, High dielectric constant oxides, Eur. Phys. J. Appl. Phys. 28(3), 265 (2004)

[28] H. Huang, , D. Bi, , B. Ning, , Y. Zhang, , Z. Zhang, , and and S. Zou, Total dose irradiation-induced degradation of hysteresis effect in partially depleted silicon-on-insulator NMOSFETs, IEEE Trans. Nucl. Sci. 60(2), 1354 (2013)

[29] S. M. George, Atomic layer deposition: An overview, Chem. Rev. 110(1), 111 (2010)

[30] S. Yang, , K. Liu, , Y. Xu, , L. Liu, , H. Li, , and and T. Zhai, Gate dielectrics integration for 2D electronics: Challenges, advances, and outlook, Adv. Mater. 35(18), 2207901 (2023)

[31] Q. H. Wang and M. C. Hersam, Room-temperature molecular-resolution characterization of self-assembled organic monolayers on epitaxial graphene, Nat. Chem. 1(3), 206 (2009)

[32] J. M. P. Alaboson, , Q. H. Wang, , J. D. Emery, , A. L. Lipson, , M. J. Bedzyk, , J. W. Elam, , M. J. Pellin, , and and M. C. Hersam, Seeding atomic layer deposition of high-κ dielectrics on epitaxial graphene with organic self-assembled monolayers, ACS Nano 5(6), 5223 (2011)

[33] Y. Yang, , T. Yang, , T. Song, , J. Zhou, , J. Chai, , L. M. Wong, , H. Zhang, , W. Zhu, , S. Wang, , and and M. Yang, Selective hydrogenation improves interface properties of high-κ dielectrics on 2D semiconductors, Nano Res. 15(5), 4646 (2022)

[34] H. Liu, , A. T. Neal, , M. Si, , Y. Du, , and and P. D. Ye, The effect of dielectric capping on few-layer phosphorene transistors: Tuning the Schottky barrier heights, IEEE Electron Device Lett. 35(7), 795 (2014)

[35] W. Li, , J. Zhou, , S. Cai, , Z. Yu, , J. Zhang, , N. Fang, , T. Li, , Y. Wu, , T. Chen, , X. Xie, , H. Ma, , K. Yan, , N. Dai, , X. Wu, , H. Zhao, , Z. Wang, , D. He, , L. Pan, , Y. Shi, , P. Wang, , W. Chen, , K. Nagashio, , X. Duan, , and and X. Wang, Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices, Nat. Electron. 2(12), 563 (2019)

[36] J. D. Wood, , S. A. Wells, , D. Jariwala, , K. S. Chen, , E. Cho, , V. K. Sangwan, , X. Liu, , L. J. Lauhon, , T. J. Marks, , and and M. C. Hersam, Effective passivation of exfoliated black phosphorus transistors against ambient degradation, Nano Lett. 14(12), 6964 (2014)

[37] E. Zhang, , W. Wang, , C. Zhang, , Y. Jin, , G. Zhu, , Q. Sun, , D. W. Zhang, , P. Zhou, , and and F. Xiu, Tunable charge-trap memory based on few-layer MoS₂, ACS Nano 9(1), 612 (2015)

[38] L. Cheng, , X. Qin, , A. T. Lucero, , A. Azcatl, , J. Huang, , R. M. Wallace, , K. Cho, , and and J. Kim, Atomic layer deposition of a high-κ dielectric on MoS₂ using trimethylaluminum and ozone, ACS Appl. Mater. Interfaces 6(15), 11834 (2014)

[39] J. H. Park, , S. Fathipour, , I. Kwak, , K. Sardashti, , C. F. Ahles, , S. F. Wolf, , M. Edmonds, , S. Vishwanath, , H. G. Xing, , S. K. Fullerton-Shirey, , A. Seabaugh, , and and A. C. Kummel, Atomic layer deposition of Al₂O₃ on WSe₂ functionalized by titanyl phthalocyanine, ACS Nano 10(7), 6888 (2016)

[40] S. Son, , S. Yu, , M. Choi, , D. Kim, , and and C. Choi, Improved high temperature integration of Al₂O₃ on MoS₂ by using a metal oxide buffer layer, Appl. Phys. Lett. 106(2), 021601 (2015)

[41] T. T. Lee, K. Chiranjeevulu, C. H. Hu, S. Pedaballi, and C. T. Lee, Improved performance of MoS₂ FETs using AlN/Al₂O₃ dielectric and Plasma Enhanced Atomic Layer Deposition (PEALD), J. Nanosci. Res. Rep. 4(1), 1 (2022)

[42] A. Dkhissi, , G. Mazaleyrat, , A. Estève, , and and M. D. Rouhani, Nucleation and growth of atomic layer deposition of HfO₂ gate dielectric layers on silicon oxide: A multiscale modelling investigation, Phys. Chem. Chem. Phys. 11(19), 3701 (2009)

[43] Q. H. Luc, , H. B. Do, , M. T. H. Ha, , C. C. Hu, , Y. C. Lin, , and and E. Y. Chang, Plasma enhanced atomic layer deposition passivated HfO₂/AlN/In_0.53Ga_0.47As MOSCAPs with sub-nanometer equivalent oxide thickness and low interface trap density, IEEE Electron Device Lett. 36(12), 1277 (2015)

[44] N. Fang and K. Nagashio, Band tail interface states and quantum capacitance in a monolayer molybdenum disulfide field-effect-transistor, J. Phys. D 51(6), 065110 (2018)

[45] J. Yang, , S. Kim, , W. Choi, , S. H. Park, , Y. Jung, , M. H. Cho, , and and H. Kim, Improved growth behavior of atomic-layer-deposited high-κ dielectrics on multilayer MoS₂ by oxygen plasma pretreatment, ACS Appl. Mater. Interfaces 5(11), 4739 (2013)

[46] X. Wang, , T. B. Zhang, , W. Yang, , H. Zhu, , L. Chen, , Q. Q. Sun, , and and D. W. Zhang, Improved integration of ultra-thin high-κ dielectrics in few-layer MoS₂ FET by remote forming gas plasma pretreatment, Appl. Phys. Lett. 110(5), 053110 (2017)

[47] X. Song, , J. Xu, , L. Liu, , P. T. Lai, , and and W. M. Tang, Improved interfacial and electrical properties of few-layered MoS₂ FETs with plasma-treated Al₂O₃ as gate dielectric, Appl. Surf. Sci. 481, 1028 (2019)

[48] J. H. Park, H. C. P. Movva, E. Chagarov, K. Sardashti, H. Chou, I. Kwak, K. T. Hu, S. K. Fullerton-Shirey, P. Choudhury, S. K. Banerjee, and A. C. Kummel, In Situ observation of initial stage in dielectric growth and deposition of ultrahigh nucleation density dielectric on two-dimensional surfaces, Nano Lett. 15(10), 6626 (2015)

[49] L. Liao and X. Zou, Interface engineering for high-performance top-gated MoS₂ field effect transistors, in: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2014), pp 1–3

[50] K. M. Price, , S. Najmaei, , C. E. Ekuma, , R. A. Burke, , M. Dubey, , and and A. D. Franklin, Plasma-enhanced atomic layer deposition of HfO₂ on monolayer, bilayer, and trilayer MoS₂ for the integration of high-κ dielectrics in two-dimensional devices, ACS Appl. Nano Mater. 2(7), 4085 (2019)

[51] H. Zhu, , R. Addou, , Q. Wang, , Y. Nie, , K. Cho, , M. J. Kim, , and and R. M. Wallace, Surface and interfacial study of atomic layer deposited Al₂O₃ on MoTe₂ and WTe₂, Nanotechnology 31(5), 055704 (2020)

[52] O. Sneh, , R. B. Clark-Phelps, , A. R. Londergan, , J. Winkler, , and and T. E. Seidel, Thin film atomic layer deposition equipment for semiconductor processing, Thin Solid Films 402(1−2), 248 (2002)

[53] C. Y. Zhu, J. K. Qin, P. Y. Huang, H. L. Sun, N. F. Sun, Y. L. Shi, L. Zhen, and C. Y. Xu, 2D indium phosphorus sulfide (In₂P₃S₉): An emerging van der Waals high‐κ dielectrics, Small 18(5), 2104401 (2022)

[54] J. Hu, A. Zheng, E. Pan, J. Chen, R. Bian, J. Li, Q. Liu, G. Cao, P. Meng, X. Jian, A. Molnar, Y. Vysochanskii, and F. Liu, 2D semiconductor SnP₂S₆ as a new dielectric material for 2D electronics, J. Mater. Chem. C 10(37), 13753 (2022)

[55] B. A. Holler, K. Crowley, M. H. Berger, and X. P. A. Gao, 2D semiconductor transistors with van der Waals oxide MoO₃ as integrated high-κ gate dielectric, Adv. Electron. Mater. 6(10), 2000635 (2020)

[56] F. Xu, , Z. Wu, , G. Liu, , F. Chen, , J. Guo, , H. Zhou, , J. Huang, , Z. Zhang, , L. Fei, , X. Liao, , and and Y. Zhou, Few-layered MnAl₂S₄ dielectrics for high-performance van der Waals stacked transistors, ACS Appl. Mater. Interfaces 14(22), 25920 (2022)

[57] L. Shen, , J. Zhou, , T. Yang, , M. Yang, , and and Y. P. Feng, High-throughput computational discovery and intelligent design of two-dimensional functional materials for various applications, Acc. Mater. Res. 3(6), 572 (2022)

[58] J. Wang, , H. Lai, , X. Huang, , J. Liu, , Y. Lu, , P. Liu, , and and W. Xie, High-κ van der Waals oxide MoO₃ as efficient gate dielectric for MoS₂ field-effect transistors, Materials (Basel) 15(17), 5859 (2022)

[59] A. Söll, , E. Lopriore, , A. Ottesen, , J. Luxa, , G. Pasquale, , J. Sturala, , F. Hájek, , V. Jarý, , D. Sedmidubský, , K. Mosina, , I. Sokolović, , S. Rasouli, , T. Grasser, , U. Diebold, , A. Kis, , and and Z. Sofer, High-κ wide-gap layered dielectric for two-dimensional van der Waals heterostructures, ACS Nano 18(15), 10397 (2024)

[60] M. R. Osanloo, , M. L. Van de Put, , A. Saadat, , and and W. G. Vandenberghe, Identification of two-dimensional layered dielectrics from first principles, Nat. Commun. 12(1), 5051 (2021)

[61] Q. A. Vu, , S. Fan, , S. H. Lee, , M. K. Joo, , W. J. Yu, , and and Y. H. Lee, Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS₂ field-effect transistors, 2D Mater. 5, 031001 (2018)

[62] T. Knobloch, , Y. Y. Illarionov, , F. Ducry, , C. Schleich, , S. Wachter, , K. Watanabe, , T. Taniguchi, , T. Mueller, , M. Waltl, , M. Lanza, , M. I. Vexler, , M. Luisier, , and and T. Grasser, The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials, Nat. Electron. 4(2), 98 (2021)

[63] J. Chen, , Z. Liu, , X. Dong, , Z. Gao, , Y. Lin, , Y. He, , Y. Duan, , T. Cheng, , Z. Zhou, , H. Fu, , F. Luo, , and and J. Wu, Vertically grown ultrathin Bi₂SiO₅ as high-κ single-crystalline gate dielectric, Nat. Commun. 14(1), 4406 (2023)

[64] Y. Zhang, J. Yu, R. Zhu, M. Wang, C. Tan, T. Tu, X. Zhou, C. Zhang, M. Yu, X. Gao, Y. Wang, H. Liu, P. Gao, K. Lai, and H. Peng, A single-crystalline native dielectric for two-dimensional semiconductors with an equivalent oxide thickness below 0.5 nm, Nat. Electron. 5(10), 643 (2022)

[65] H. Y. Lan, J. Appenzeller, and Z. Chen, Dielectric interface engineering for high-performance monolayer MoS. transistors via hBN interfacial layer and Ta seeding, in: 2022 International Electron Devices Meeting (IEDM), 2022, pp 7.7.1–7.7.4

[66] J. K. Huang, , Y. Wan, , J. Shi, , J. Zhang, , Z. Wang, , W. Wang, , N. Yang, , Y. Liu, , C. H. Lin, , X. Guan, , L. Hu, , Z. L. Yang, , B. C. Huang, , Y. P. Chiu, , J. Yang, , V. Tung, , D. Wang, , K. Kalantar-Zadeh, , T. Wu, , X. Zu, , L. Qiao, , L. J. Li, , and and S. Li, High-κ perovskite membranes as insulators for two-dimensional transistors, Nature 605(7909), 262 (2022)

[67] Y. Pan, , K. Jia, , K. Huang, , Z. Wu, , G. Bai, , J. Yu, , Z. Zhang, , Q. Zhang, , and and H. Yin, Near-ideal subthreshold swing MoS₂ back-gate transistors with an optimized ultrathin HfO₂ dielectric layer, Nanotechnology 30(9), 095202 (2019)

[68] C. Zhang, , T. Tu, , J. Wang, , Y. Zhu, , C. Tan, , L. Chen, , M. Wu, , R. Zhu, , Y. Liu, , H. Fu, , J. Yu, , Y. Zhang, , X. Cong, , X. Zhou, , J. Zhao, , T. Li, , Z. Liao, , X. Wu, , K. Lai, , B. Yan, , P. Gao, , Q. Huang, , H. Xu, , H. Hu, , H. Liu, , J. Yin, , and and H. Peng, Single-crystalline van der Waals layered dielectric with high dielectric constant, Nat. Mater. 22(7), 832 (2023)

[69] B. Chamlagain, , Q. Cui, , S. Paudel, , M. M. C. Cheng, , P. Y. Chen, , and and Z. Zhou, Thermally oxidized two-dimensional TaS₂ as a high-κ gate dielectric for MoS₂ field-effect transistors, 2D Mater. 4, 031002 (2017)

[70] K. A. Patel, , R. W. Grady, , K. K. H. Smithe, , E. Pop, , and and R. Sordan, Ultra-scaled MoS₂ transistors and circuits fabricated without nanolithography, 2D Mater. 7, 015018 (2019)

[71] Y. Y. Illarionov, , A. G. Banshchikov, , D. K. Polyushkin, , S. Wachter, , T. Knobloch, , M. Thesberg, , L. Mennel, , M. Paur, , M. Stöger-Pollach, , A. Steiger-Thirsfeld, , M. I. Vexler, , M. Waltl, , N. S. Sokolov, , T. Mueller, , and and T. Grasser, Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors, Nat. Electron. 2(6), 230 (2019)

[72] M. Sebek, , Z. Wang, , N. G. West, , M. Yang, , D. C. J. Neo, , X. Su, , S. Wang, , J. Pan, , N. T. K. Thanh, , and and J. Teng, Van der Waals enabled formation and integration of ultrathin high-κ dielectrics on 2D semiconductors, npj 2D Mater. Appl. 8, 1 (2024)

[73] A. J. Yang, , K. Han, , K. Huang, , C. Ye, , W. Wen, , R. Zhu, , R. Zhu, , J. Xu, , T. Yu, , P. Gao, , Q. Xiong, , and and X. Renshaw Wang, Van der Waals integration of high-κ perovskite oxides and two-dimensional semiconductors, Nat. Electron. 5(4), 233 (2022)

[74] Z. Lu, , Y. Chen, , W. Dang, , L. Kong, , Q. Tao, , L. Ma, , D. Lu, , L. Liu, , W. Li, , Z. Li, , X. Liu, , Y. Wang, , X. Duan, , L. Liao, , and and Y. Liu, Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration, Nat. Commun. 14(1), 2340 (2023)

[75] T. Li, T. Tu, Y. Sun, H. Fu, J. Yu, L. Xing, Z. Wang, H. Wang, R. Jia, J. Wu, C. Tan, Y. Liang, Y. Zhang, C. Zhang, Y. Dai, C. Qiu, M. Li, R. Huang, L. Jiao, K. Lai, B. Yan, P. Gao, and H. Peng, A native oxide high-κ gate dielectric for two-dimensional electronics, Nat. Electron. 3(8), 473 (2020)

[76] K. Liu, B. Jin, W. Han, X. Chen, P. Gong, L. Huang, Y. Zhao, L. Li, S. Yang, X. Hu, J. Duan, L. Liu, F. Wang, F. Zhuge, and T. Zhai, A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film, Nat. Electron. 4(12), 906 (2021)

[77] O. Song, D. Rhee, J. Kim, Y. Jeon, V. Mazánek, A. Söll, Y. A. Kwon, J. H. Cho, Y. -H. Kim, Z. Sofer, and J. Kang, All inkjet-printed electronics based on electrochemically exfoliated two-dimensional metal, semiconductor, and dielectric, npj 2D Mater. Appl. 6, 1 (2022)

[78] A. Bastola, , Y. He, , J. Im, , G. Rivers, , F. Wang, , R. Worsley, , J. S. Austin, , O. Nelson-Dummett, , R. D. Wildman, , R. Hague, , C. J. Tuck, , and and L. Turyanska, Formulation of functional materials for ink-jet printing: A pathway towards fully 3D printed electronics, Materials Today Electronics 6, 100058 (2023)

[79] S. Lai, , S. Byeon, , S. K. Jang, , J. Lee, , B. H. Lee, , J. H. Park, , Y. H. Kim, , and and S. Lee, HfO₂/HfS₂ hybrid heterostructure fabricated via controllable chemical conversion of two-dimensional HfS₂, Nanoscale 10(39), 18758 (2018)

[80] T. T. T. Can and W. S. Choi, Improved electrical properties of EHD jet-patterned MoS₂ thin-film transistors with printed Ag electrodes on a high-κ dielectric, Nanomaterials (Basel) 13(1), 194 (2023)

[81] T. Carey, , A. Arbab, , L. Anzi, , H. Bristow, , F. Hui, , S. Bohm, , G. Wyatt-Moon, , A. Flewitt, , A. Wadsworth, , N. Gasparini, , J. M. Kim, , M. Lanza, , I. McCulloch, , R. Sordan, , and and F. Torrisi, Inkjet printed circuits with 2D semiconductor inks for high‐performance electronics, Adv. Electron. Mater. 7(7), 2100112 (2021)

[82] K. Cho, , T. Lee, , and and S. Chung, Inkjet printing of two-dimensional van der Waals materials: A new route towards emerging electronic device applications, Nanoscale Horiz. 7(10), 1161 (2022)

[83] N. Peimyoo, , M. D. Barnes, , J. D. Mehew, , A. De Sanctis, , I. Amit, , J. Escolar, , K. Anastasiou, , A. P. Rooney, , S. J. Haigh, , S. Russo, , M. F. Craciun, , and and F. Withers, Laser-writable high-κ dielectric for van der Waals nanoelectronics, Sci. Adv. 5(1), eaau0906 (2019)

[84] Y. Zhang, , D. Venkatakrishnarao, , M. Bosman, , W. Fu, , S. Das, , F. Bussolotti, , R. Lee, , S. L. Teo, , D. Huang, , I. Verzhbitskiy, , Z. Jiang, , Z. Jiang, , J. Chai, , S. W. Tong, , Z. E. Ooi, , C. P. Y. Wong, , Y. S. Ang, , K. E. J. Goh, , and and C. S. Lau, Liquid−metal-printed ultrathin oxides for atomically smooth 2D material heterostructures, ACS Nano 17(8), 7929 (2023)

[85] P. Luo, , C. Liu, , J. Lin, , X. Duan, , W. Zhang, , C. Ma, , Y. Lv, , X. Zou, , Y. Liu, , F. Schwierz, , W. Qin, , L. Liao, , J. He, , and and X. Liu, Molybdenum disulfide transistors with enlarged van der Waals gaps at their dielectric interface via oxygen accumulation, Nat. Electron. 5(12), 849 (2022)

[86] T. E. Lee, Y. C. Su, B. J. Lin, Y. X. Chen, W. S. Yun, P. H. Ho, J. F. Wang, S. K. Su, C. F. Hsu, P. S. Mao, Y. C. Chang, C. H. Chien, B. H. Liu, C. Y. Su, C. C. Kei, H. Wang, H. S. Philip Wong, T. Y. Lee, W. H. Chang, C. C. Cheng, and I. P. Radu, Nearly ideal subthreshold swing in monolayer MoS₂ top-gate nFETs with scaled EOT of . nm, in: 2022 International Electron Devices Meeting (IEDM), 2022, pp 7.4.1–7.4.4

[87] G. Lin, , M. Q. Zhao, , M. Jia, , J. Zhang, , P. Cui, , L. Wei, , H. Zhao, , A. T. C. Johnson, , L. Gundlach, , and and Y. Zeng, Performance enhancement of monolayer MoS₂ transistors by atomic layer deposition of high-κ dielectric assisted by Al₂O₃ seed layer, J. Phys. D Appl. Phys. 53(10), 105103 (2020)

[88] Y. Xu, , T. Liu, , K. Liu, , Y. Zhao, , L. Liu, , P. Li, , A. Nie, , L. Liu, , J. Yu, , X. Feng, , F. Zhuge, , H. Li, , X. Wang, , and and T. Zhai, Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors, Nat. Mater. 22(9), 1078 (2023)

[89] J. Pang, , A. Bachmatiuk, , Y. Yin, , B. Trzebicka, , L. Zhao, , L. Fu, , R. G. Mendes, , T. Gemming, , Z. Liu, , and and M. H. Rummeli, Applications of phosphorene and black phosphorus in energy conversion and storage devices, Adv. Energy Mater. 8(8), 1702093 (2018)

[90] M. Sup Choi, , G. H. Lee, , Y. J. Yu, , D. Y. Lee, , S. Hwan Lee, , P. Kim, , J. Hone, , and and W. Jong Yoo, Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices, Nat. Commun. 4(1), 1624 (2013)

[91] T. Roy, , M. Tosun, , J. S. Kang, , A. B. Sachid, , S. B. Desai, , M. Hettick, , C. C. Hu, , and and A. Javey, Field-effect transistors built from all two-dimensional material components, ACS Nano 8(6), 6259 (2014)

[92] G. H. Lee, , X. Cui, , Y. D. Kim, , G. Arefe, , X. Zhang, , C. H. Lee, , F. Ye, , K. Watanabe, , T. Taniguchi, , P. Kim, , and and J. Hone, Highly stable, dual-gated MoS₂ transistors encapsulated by hexagonal boron nitride with gate-controllable contact, resistance, and threshold voltage, ACS Nano 9(7), 7019 (2015)

[93] X. Cui, , G. H. Lee, , Y. D. Kim, , G. Arefe, , P. Y. Huang, , C. H. Lee, , D. A. Chenet, , X. Zhang, , L. Wang, , F. Ye, , F. Pizzocchero, , B. S. Jessen, , K. Watanabe, , T. Taniguchi, , D. A. Muller, , T. Low, , P. Kim, , and and J. Hone, Multi-terminal transport measurements of MoS₂ using a van der Waals heterostructure device platform, Nat. Nanotechnol. 10(6), 534 (2015)

[94] Z. Zhang, , X. Ji, , J. Shi, , X. Zhou, , S. Zhang, , Y. Hou, , Y. Qi, , Q. Fang, , Q. Ji, , Y. Zhang, , M. Hong, , P. Yang, , X. Liu, , Q. Zhang, , L. Liao, , C. Jin, , Z. Liu, , and and Y. Zhang, Direct chemical vapor deposition growth and band-gap characterization of MoS₂/h-BN van der Waals heterostructures on Au foils, ACS Nano 11(4), 4328 (2017)

[95] M. Mattinen, , G. Popov, , M. Vehkamäki, , P. J. King, , K. Mizohata, , P. Jalkanen, , J. Räisänen, , M. Leskelä, , and M. Ritala, , and Atomic layer deposition of emerging 2D semiconductors, HfS₂ and ZrS₂, for optoelectronics, Chem. Mater. 31(15), 5713 (2019)

[96] M. J. Mleczko, , C. Zhang, , H. R. Lee, , H. H. Kuo, , B. Magyari-Köpe, , R. G. Moore, , Z. X. Shen, , I. R. Fisher, , Y. Nishi, , and and E. Pop, HfSe₂ and ZrSe₂: Two-dimensional semiconductors with native high-κ oxides, Sci. Adv. 3(8), e1700481 (2017)

[97] Y. Jin, , J. Sun, , L. Zhang, , J. Yang, , Y. Wu, , B. You, , X. Liu, , K. Leng, , and and S. Liu, Controllable oxidation of ZrS₂ to prepare high‐κ, single‐crystal m‐ZrO₂ for 2D electronics, Adv. Mater. 35(18), 2212079 (2023)

[98] L. Yang, R. Jaramillo, R. K. Kalia, A. Nakano, and P. Vashishta, Pressure-dependent layer-by-layer oxidation of ZrS₂(001) surface, arXiv: 2023)

[99] Q. Smets, G. Arutchelvan, J. Jussot, D. Verreck, I. Asselberghs, A. N. Mehta, A. Gaur, D. Lin, S. E. Kazzi, B. Groven, M. Caymax, and I. Radu, Ultra-scaled MOCVD MoS₂ MOSFETs with 42 nm contact pitch and 250 μA/μm drain current, in: 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp 23.2.1–23.2.4

[100] H. B. Jeon, , G. H. Shin, , K. J. Lee, , and and S. Y. Choi, Vertical‐tunneling field‐effect transistor based on WSe₂–MoS₂ heterostructure with ion gel dielectric, Adv. Electron. Mater. 6(7), 2000091 (2020)

[101] K. S. Novoselov, A. Mishchenko, A. Carvalho, and A. H. Castro Neto, 2D materials and van der Waals heterostructures, Science 353(6298), aac9439 (2016)

[102] J. Cai, , X. Han, , X. Wang, , and and X. Meng, Atomic layer deposition of two-dimensional layered materials: Processes, growth mechanisms, and characteristics, Matter 2(3), 587 (2020)

[103] D. Akinwande, , C. Huyghebaert, , C. H. Wang, , M. I. Serna, , S. Goossens, , L. J. Li, , H. S. P. Wong, , and and F. H. L. Koppens, Graphene and two-dimensional materials for silicon technology, Nature 573(7775), 507 (2019)

[104] H. Abuzaid, , N. X. Williams, , and and A. D. Franklin, How good are 2D transistors? An application-specific benchmarking study, Appl. Phys. Lett. 118(3), 030501 (2021)

[105] F. Zhuo, , J. Wu, , B. Li, , M. Li, , C. L. Tan, , Z. Luo, , H. Sun, , Y. Xu, , and and Z. Yu, Modifying the power and performance of 2-dimensional MoS₂ field effect transistors, Research 6, 0057 (2023)

[106] Y. Liu, , X. Duan, , H. J. Shin, , S. Park, , Y. Huang, , and and X. Duan, Promises and prospects of two-dimensional transistors, Nature 591(7848), 43 (2021)

[107] S. Zeng, , C. Liu, , and and P. Zhou, Transistor engineering based on 2D materials in the post-silicon era, Nat. Rev. Electr. Eng. 1, 335 (2024)

[108] C. Liu, , H. Chen, , S. Wang, , Q. Liu, , Y. G. Jiang, , D. W. Zhang, , M. Liu, , and and P. Zhou, Two-dimensional materials for next-generation computing technologies, Nat. Nanotechnol. 15(7), 545 (2020)

[109] Y. Liu, N. O. Weiss, X. Duan, H. -C. Cheng, Y. Huang, and X. Duan, Van der Waals heterostructures and devices, Nat. Rev. Mater. 1, 1 (2016)

[110] Y. Liu, , Y. Huang, , and and X. Duan, Van der Waals integration before and beyond two-dimensional materials, Nature 567(7748), 323 (2019)

[111] X. Zhang, , Y. Zhang, , H. Yu, , H. Zhao, , Z. Cao, , Z. Zhang, , and and Y. Zhang, Van der Waals‐interface‐dominated all‐2D electronics, Adv. Mater. 35(50), 2207966 (2023)

[112] S. Kim, , J. Seo, , J. Choi, , and and H. Yoo, Vertically integrated electronics: New opportunities from emerging materials and devices, Nano-Micro Lett. 14(1), 201 (2022)

[113] L. Liu and T. Zhai, Wafer-scale vertical van der Waals heterostructures, InfoMat 3(1), 3 (2021)

[114] I. E. Dzyaloshinskii, , E. M. Lifshitz, , and and L. P. Pitaevskii, The general theory of van der Waals forces, Adv. Phys. 10(38), 165 (1961)

[115] A. Cabrero-Vilatela, , J. A. Alexander-Webber, , A. A. Sagade, , A. I. Aria, , P. Braeuninger-Weimer, , M. B. Martin, , R. S. Weatherup, , and and S. Hofmann, Atomic layer deposited oxide films as protective interface layers for integrated graphene transfer, Nanotechnology 28(48), 485201 (2017)

[116] S. B. Desai, , S. R. Madhvapathy, , M. Amani, , D. Kiriya, , M. Hettick, , M. Tosun, , Y. Zhou, , M. Dubey, , J. W. Ager, , D. Chrzan, , and and A. Javey, Gold‐mediated exfoliation of ultralarge optoelectronically-perfect monolayers, Adv. Mater. 28, 4053 (2016)

[117] B. Wang, , W. Huang, , L. Chi, , M. Al-Hashimi, , T. J. Marks, , and and A. Facchetti, High-κ gate dielectrics for emerging flexible and stretchable electronics, Chem. Rev. 118, 5690 (2018)

[118] R. P. Ortiz, , A. Facchetti, , and and T. J. Marks, High-κ organic, inorganic, and hybrid dielectrics for low-voltage organic field-effect transistors, Chem. Rev. 110, 205 (2010)

[119] A. V. Zaretski, , H. Moetazedi, , C. Kong, , E. J. Sawyer, , S. Savagatrup, , E. Valle, , T. F. O’Connor, , A. D. Printz, , and and D. J. Lipomi, Metal-assisted exfoliation (MAE): Green, roll-to-roll compatible method for transferring graphene to flexible substrates, Nanotechnology 26, 045301 (2015)

[120] A. V. Zaretski and D. J. Lipomi, Processes for non-destructive transfer of graphene: Widening the bottleneck for industrial scale production, Nanoscale 7, 9963 (2015)

[121] X. Cui, , Z. Kong, , E. Gao, , D. Huang, , Y. Hao, , H. Shen, , C. Di, , Z. Xu, , J. Zheng, , and and D. Zhu, Rolling up transition metal dichalcogenide nanoscrolls via one drop of ethanol, Nat. Commun. 9, 1301 (2018)

[122] A. Gurarslan, , Y. Yu, , L. Su, , Y. Yu, , F. Suarez, , S. Yao, , Y. Zhu, , M. Ozturk, , Y. Zhang, , and and L. Cao, Surface-energy-assisted perfect transfer of centimeter-scale monolayer and few-layer MoS₂ films onto arbitrary substrates, ACS Nano 8, 11522 (2014)

[123] L. Niinistö, , M. Nieminen, , J. Päiväsaari, , J. Niinistö, , M. Putkonen, , and and M. Nieminen, Advanced electronic and optoelectronic materials by Atomic Layer Deposition: An overview with special emphasis on recent progress in processing of high-κ dielectrics and other oxide materials, physica status solidi (a) 201, 1443 (2004)

[124] M. Leskelä and M. Ritala, Atomic layer deposition chemistry: Recent developments and future challenges, Angewandte Chemie International Edition 42, 5548 (2003)

[125] M. D. Groner and S. M. George, High-κ dielectrics grown by atomic layer deposition, in: Interlayer Dielectrics for Semiconductor Technologies, edited by S. P. Murarka, M. Eizenberg, and A. K. Sinha, Academic Press, 2003, pp 327–348

[126] J. T. Gaskins, , P. E. Hopkins, , D. R. Merrill, , S. R. Bauers, , E. Hadland, , D. C. Johnson, , D. Koh, , J. H. Yum, , S. Banerjee, , B. J. Nordell, , M. M. Paquette, , A. N. Caruso, , W. A. Lanford, , P. Henry, , L. Ross, , H. Li, , L. Li, , M. French, , A. M. Rudolph, , and and S. W. King, Investigation and review of the thermal, mechanical, electrical, optical, and structural properties of atomic layer deposited high-κ dielectrics: Beryllium oxide, aluminum oxide, hafnium oxide, and aluminum nitride, ECS J. Solid State Sci. Technol. 6, N189 (2017)

[127] A. Eskandari Nasrabad, and and R. Laghaei, Computational studies on thermodynamic properties, effective diameters, and free volume of argon using an ab initio potential, J. Chem. Phys. 125, 084510 (2006)

[128] J. Hermann, , R. A. Jr. DiStasio, , and and A. Tkatchenko, First-principles models for van der Waals interactions in molecules and materials: Concepts, theory, and applications, Chem. Rev. 117, 4714 (2017)

[129] K. Liu and T. Zhai, Emergence of two-dimensional inorganic molecular crystals, Acc. Mater. Res. 5(6), 665 (2024)

[130] A. Jabeen, , A. Majid, , M. Alkhedher, , S. Haider, , and and M. S. Akhtar, Impacts of structural downscaling of inorganic molecular crystals ‒ A DFT study of Sb₂O₃, Mater. Sci. Semicond. Process. 166, 107729 (2023)

[131] W. Han, , P. Huang, , L. Li, , F. Wang, , P. Luo, , K. Liu, , X. Zhou, , H. Li, , X. Zhang, , Y. Cui, , and and T. Zhai, Two-dimensional inorganic molecular crystals, Nat. Commun. 10, 4728 (2019)

[132] T. Kang, J. Park, H. Jung, H. Choi, S. -M. Lee, N. Lee, R. -G. Lee, G. Kim, S. -H. Kim, H. Kim, C. -W. Yang, J. Jeon, Y. -H. Kim, and S. Lee, High-κ dielectric (HfO₂)/2D semiconductor (HfSe₂) gate stack for low-power steep-switching computing devices, Adv. Mater. 36(26), 2312747

[133] C. Lee, S. Rathi, M. A. Khan, D. Lim, Y. Kim, S. J. Yun, D. -H. Youn, K. Watanabe, T. Taniguchi, and G. -H. Kim, Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS₂ flake based field effect transistors on SiO₂ and hBN substrates, Nanotechnology 29, 335202 (2018)

[134] X. Han, , J. Lin, , J. Liu, , N. Wang, , and and D. Pan, Effects of hexagonal boron nitride encapsulation on the electronic structure of few-layer MoS₂, J. Phys. Chem. C 123, 14797 (2019)

[135] S. Fiore, , C. Klinkert, , F. Ducry, , J. Backman, , and and M. Luisier, Influence of the hBN dielectric layers on the quantum transport properties of MoS2 transistors, Materials 15, 1062 (2022)

[136] A. Shivayogimath, , P. R. Whelan, , D. M. A. Mackenzie, , B. Luo, , D. Huang, , D. Luo, , M. Wang, , L. Gammelgaard, , H. Shi, , R. S. Ruoff, , P. Bøggild, , and and T. J. Booth, Do-it-yourself transfer of large-area graphene using an office laminator and water, Chem. Mater. 31, 2328 (2019)

[137] H. Xu, , H. Zhang, , Z. Guo, , Y. Shan, , S. Wu, , J. Wang, , W. Hu, , H. Liu, , Z. Sun, , C. Luo, , X. Wu, , Z. Xu, , D. W. Zhang, , W. Bao, , and and P. Zhou, High-performance wafer-scale MoS₂ transistors toward practical application, Small 14, 1803465 (2018)

[138] A. Quellmalz, , X. Wang, , S. Sawallich, , B. Uzlu, , M. Otto, , S. Wagner, , Z. Wang, , M. Prechtl, , O. Hartwig, , S. Luo, , G. S. Duesberg, , M. C. Lemme, , K. B. Gylfason, , N. Roxhed, , G. Stemme, , and and F. Niklaus, Large-area integration of two-dimensional materials and their heterostructures by wafer bonding, Nat. Commun. 12, 917 (2021)

[139] Y. Kim, T. Kim, J. Lee, Y. S. Choi, J. Moon, S. Y. Park, T. H. Lee, H. K. Park, S. A. Lee, M. S. Kwon, H. -G. Byun, J. -H. Lee, M. -G. Lee, B. H. Hong, and H. W. Jang, Tailored graphene micropatterns by wafer-scale direct transfer for flexible chemical sensor platform, Adv. Mater. 33, 2004827 (2021)

[140] P. S. Borhade, R. Raman, Z. -L. Yen, Y. -P. Hsieh, and M. Hofmann, Transferrable alumina membranes as high-performance dielectric for flexible 2D materials devices, Adv. Electron. Mater. 10, 2300783 (2024)

[141] H. Yu, M. Liao, W. Zhao, G. Liu, X. J. Zhou, Z. Wei, X. Xu, K. Liu, Z. Hu, K. Deng, S. Zhou, J. -A. Shi, L. Gu, C. Shen, T. Zhang, L. Du, L. Xie, J. Zhu, W. Chen, R. Yang, D. Shi, and G. Zhang, Wafer-scale growth and transfer of highly-oriented monolayer MoS₂ continuous films, ACS Nano 11, 12001 (2017)

Declarations

The authors declare that they have no competing interests and there are no conflicts.

Acknowledgements

M. Y. acknowledges the funding support from the National Key R&D Program of the Ministry of Science and Technology of China (Project No. 2022YFA1203804), the Hong Kong Polytechnic University (Project Nos. P0034827, P0042711, P0039734, P0039679, URIS2023-050, and URIS2023-052), PolyU RCNN (Project No. P0048122), and Research Grants Council, Hong Kong (Project Nos. P0046939 and P0045061). We thank the computing resources from the National Supercomputer Centre, Singapore. T. Z. was supported by the National Natural Science Foundation of China (Grant No. 12204346).

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