Low-power three-stage amplifier using active-feedback Miller capacitor and serial RC frequency compensation

Abstract

A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor R _z and the capacitor C _z under fixed power and small compensation capacitor C _a, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 pF and 2 nF, respectively. The post-layout simulation results show that the amplifier driving the 500 pF capacitive load can achieve a gain of 113 dB, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 nF capacitive load, the amplifier has a gain of 102 dB, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 pF and 1.03 pF. The better figures-of-merits are 108 750 and 205 113(MHz×pF/mW). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at C _L=500 pF and C _a=1.1 pF.

Keywords

multistage amplifier / frequency compensation / gain-bandwidth product / active-feedback

References

[1] Leung K N, Mok P K T. A capacitor-free CMOS lowdropout regulator with damping-factor-control frequency compensation [J]. IEEE Journal of Solid-State Circuits, 2003, 38(38): 1691-1702.

[2] Lau S K, Mok P K T, Leung K N. A low-dropout regulator for SoC with Q-reduction [J]. IEEE Journal of Solid-State Circuits, 2007, 42(42): 658-664.

[3] Ho E N Y, Mok P K T. A capacitor-less CMOS activefeedback low-dropout regulator with slew-rate enhancement for portable on-chip application [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2010, 57(57): 80-84.

[4] Aminzadeh H. Three-stage nested-Miller-compensated operational amplifiers: Analysis, design, and optimization based on settling time [J]. International Journal of Circuit Theory and Applications, 2011, 39(39): 573-587.

[5] Eschauzier R G H, Huijsing J H. Frequency Compensation Techniques for Low-Power Operational Amplifiers [M], 1995, USA: Springer-Verlag

[6] Eschauzier R G H, Kerklaan L P T, Huijsing J H. A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure [J]. IEEE Journal of Solid-State Circuits, 1992, 27(27): 1709-1717.

[7] Huijsing J H. Multistage Amplifier with Capacitive Nesting for Frequency Compensation: USA, 4559502 [P]. 1985-12-17.

[8] Fan Y, Embabi S H K, Sanchez-Sinencio E. A multistage amplifier topology with nested Gm-C compensation for low-voltage application [C]. IEEE International Solid-State Circuits Conference, 1997, USA: San Francisco.

[9] Fan X H, Mishra C, Sanchez-Sinencio E. Single Miller capacitor frequency compensation technique for lowpower multistage amplifiers [J]. IEEE Journal of Solid-State Circuits, 2005, 40(40): 584-592.

[10] Peng X H, Sansen W, Hou L G, et al. Impedance adapting compensation for low-power multistage amplifiers [J]. IEEE Journal of Solid-State Circuits, 2011, 46(46): 445-451.

[11] Ahuja B K. An improved frequency compensation technique for CMOS operational amplifiers [J]. IEEE Journal of Solid-State Circuits, 1983, 18(18): 629-633.

[12] Lee H, Mok P K T. Active-feedback frequencycompensation technique for low-power multistage amplifiers [J]. IEEE Journal of Solid-State Circuits, 2003, 38(38): 511-520.

[13] Lee H, Mok P K T. Advances in active-feedback frequency compensation with power optimization and transient improvement [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(51): 1690-1696.

[14] Leung K N, Mok P K T, Ki W H, et al. Three-stage large capacitive load amplifier with damping-factor-control frequency compensation [J]. IEEE Journal of Solid-State Circuits, 2000, 35(35): 221-230.

[15] Lee H, Leung K N, Mok P K T. A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation [J]. IEEE Journal of Solid-State Circuits, 2003, 38(38): 1739-1744.

[16] Guo S, Lee H. Dual active-capacitive-feedback compensation for low-power large-capacitive-load three-stage amplifiers [J]. IEEE Journal of Solid-State Circuits, 2011, 46(46): 452-464.

[17] Chong S S, Chan P K. Cross feedforward cascode compensation for low-power three-stage amplifier with large capacitive load [J]. IEEE Journal of Solid-State Circuits, 2012, 47(47): 2227-2234.

[18] Yan Z S, Mak P I, Law M, et al. A 0. 016-mm² 144-µW three-stage amplifier capable of driving 1-to-15 nF capacitive load with >0. 95-MHz GBW [J]. IEEE Journal of Solid-State Circuits, 2013, 48(48): 527-540.

[19] Qu W Y, Im J P, Kim H S, et al. A 0. 9 V 6. 3 µW multistage amplifier driving 500 pF capacitive load with 1. 34 MHz GBW [C]. IEEE International Solid-State Circuits Conference, 2014, USA: San Francisco.

[20] Kamath B Y T, Meyer R G, Gray P R. Relationship between frequency response and settling time of operational amplifiers [J]. IEEE Journal of Solid-State Circuits, 1974, 9(9): 347-352.

[21] Bult K, Geelen G J G M. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain [J]. IEEE Journal of Solid-State Circuits, 1990, 25(25): 1379-1384.

[22] Palumbo G, Pennisi S. Design methodology and advances in nested-Miller compensation [J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2002, 49(49): 893-903.

[23] Mojarad M, Yavari M. A low-power four-stage amplifier for driving large capacitive loads [J]. International Journal of Circuit Theory and Applications, 2014, 42(42): 978-988.