Stability analysis of CPLL with loop delay

Abstract

In this paper, a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay. The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method. The simulation results under SPECTRE show that, due to the sampling nature of CPLL, the traditional s-domain analysis is unable to predict its jitter peaking accurately, especially when the loop delay is taken into consideration. The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way. The stability limit of the wide bandwidth CPLL with loop delay is calculated. The circuit simulation results agree well with mathematical analysis.

Keywords

charge-pump based phase-locked loop (CPLL) / third-order / loop delay / stability analysis / z-domain model

References

[1] Murphy D, Gu Q J, Wu Y C, et al. A low phase noise, wideband and compact CMOS PLL for use in heterodyne 802.15.3c transceiver [J]. IEEE Journal of Solid-State Circuits, 2012, 46(7): 1606-1617.

[2] Yun S J, Lee H D, Kim K D, et al. Differentially-tuned lowspur PLL using 65 nm CMOS process [J]. Electronics Letters, 2011, 47(6): 369-371.

[3] Pohl N, Jaeschke T, Aufinger K. An ultra-wideband 80 GHz FMCW rader system using a SiGe bipolar transceiver chip stabilized by a fractional-N PLL synthesizer [J]. IEEE Transactions on Microwave Theory and Techniques, 2012, 60(3): 757-765.

[4] Ma X P, Zhang W, Liu Y. A fully integrated multi-band LCVCO based on CMOS technology [J]. Journal of Circuits, Systems, and Computers, 2010, 19(6): 1299-1305.

[5] Jee D W, Seo Y H, Park H J, et al. A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC [J]. IEEE Journal of Solid-State Circuits, 2012, 47(4): 875-883.

[6] Gardner F M. Charge-pump phase-lock loops [J]. IEEE Transactions on Communications, 1980, 28(11): 1849-1858.

[7] Hein J P, Scott J W. z-domain model for discrete-time PLLs [J]. IEEE Transactions on Circuits and Systems, 1988, 35(11): 1393-1400.

[8] Hanumolu P K, Brownlee M, Mayaram K, et al. Analysis of charge-pump phase-locked loops [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(9): 1665-1674.

[9] de Gloria A, Grosso D, Olivieri N, et al. A novel stability analysis of a PLL for timing recovery in hard disk drives [J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1999, 46(8): 1026-1031..

[10] Bergmans J W M. Effect of loop delay on stability of discrete-time PLL [J]. IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications I, 1995, 42(4): 229 231

[11] Bergmans J W M. Effect of loop delay on phase margin of first-order and second-order control loops [J]. IEEE Transactions on Circuits and Systems: Express Briefs II, 2005, 52(10): 621-625.

[12] Nian X H. Stability of linear systems with time-varying delays: An Lyapunov functional approach [C]. IEEE Proceedings of the American Control Conference. Denver, USA, 2003

[13] Hu T S, Lin Z L. Absolute stability analysis of discretetime systems with composite quadratic Lyapunov functions [J]. IEEE Transactions on Automatic Control, 2005, 50(6): 781 797

[14] van Paemel M. Analysis of a charge pump PLL: A new model [J]. IEEE Transactions on Communications, 1994, 42(7): 2490-2498.

[15] Wang Z D. An analysis of charge-pump phase-locked loops [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2005, 52(10): 2128 2138