Digital self-calibration technique based on 14-bit SAR ADC

Abstract

An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter (SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.

Keywords

SAR ADC / capacitor mismatch / error correction technique / split capacitor DAC

References

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