High speed column-parallel CDS/ADC circuit with nonlinearity compensation for CMOS image sensors

Abstract

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper. The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a three-phase column-parallel circuit based on two floating gate inverters and switched-capacitor network. The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step. A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step, which can reduce the clock step from 2 ⁿ to 2^(n/2+1). The floating gate inverters are implemented to reduce the power consumption. Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter, which can equalize the coupling path in three phases of the proposed circuit. This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18 μm process. Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10 MHz. The power consumption of this circuit is less than 36.5 μW with a 3.3 V power supply. The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Keywords

CMOS image sensor / two-step single-slope ADC / nonlinear offset compensation / high speed / low power consumption

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