Double-folding paper-based generator for mechanical energy harvesting

Abstract

Paper-based generators are essential elements for building all paper-based systems. To obtain robust paper-based generators with outstanding high power outputs, this paper introduced a new type of double-folding paper-based generator by folding two paper components together. The output performance levels of the double-folding generator were twice higher than that of the single-folding and parallel-plate generators. A peak power of ~3.24 mW was achieved under a stimulating frequency of 3 Hz. Furthermore, 47 light-emitting diodes (LEDs) were lit directly by a double-folding paper-based generator assembled to the crack of a door that opens and closes. This finding indicated the potential applications of the double-folding generator in the production of door ornaments or for security in places where doors frequently open and close.

Keywords

paper-based generator / double-folding / electret / electrostatic induction

1 Introduction

The recent discussion on amorphous oxide semiconductor (AOS) is extensive around the world. Thin film transistor using amorphous indium gallium zinc oxide as active layer (a-IGZO-TFT) has become one of the most popular topic due to its high mobility, high light transmission and low temperature process.

The electrical properties of a-IGZO-TFT are mainly determined by the contents of In and Ga in the active layer. On the one hand, the mobility of device enhances with the increase of In content, while the off current increases and the sub-threshold swing becomes worse at the same time. On the other hand, the increase of Ga content results in the decrease of off current and a better sub-threshold swing, but it also reduce the mobility of device. In order to resolve this problem, double active layer structures are proposed. In these structures, the material of high mobility and low electrical conductivity is used as front active layer, and the material of low mobility and high electrical conductivity is used as back active layer, such as IGZO/IGZO-N [ 1], IGZO/ZIO [ 2], ITO/IGZO [ 3], IGZO/CuGaInZnO [ 4], HfInZnO/HfInZnO (different In content) [ 5]. By using an ITO/IGZO double active stack, excellent TFT properties with a high mobility of 10 cm²/(V·S), suitable threshold voltage (V_th) of 0.5 V, and a sub-threshold swing (SS) of 0.25 V/decade were demonstrated. Marrs et al. switched IGZO single layer structure to the IZO/IGZO dual active layer structure, the saturation mobility increased from 1.2 to 18 cm²/(V·S) [ 2]. Maeng et al. effectively reduced the sub-threshold photocurrent by modulating the cation composition of the back channel layer [ 5]. As a result, the mobility of double active layers device is improved significantly compare to the single layer one, and the electrical stability has also been enhanced.

It is clear that the device with double active layers have better electrical performance. However, most researches of double active layer device only focused on some fixed structures, few of them take the thickness variation of each active layers and the interface between the two active layers into consideration. So we used ATLAS 2D device simulator of SILVACO for device simulation of inverted-staggered a-IGZO-TFT with double active layers, based on the density of states (DOS) model. In-rich front active layer was used to enhance the mobility and operating current, and the In-poor back active layer was used to improve the sub-threshold swing. The change of the device performance caused by modulating the thickness of each active layers and the position of the interface between the two active layers was investigated.

2 Device simulation

DOS we used in this paper is an important concept in amorphous thin film. It represents the number of states near some particular energy level. With Fermi-Dirac statistic, the effect carrier concentration of fixed material can be calculated. In a-IGZO system, the acceptor like conduction band-tail states g_ta, the donor-like valence band-tail states g_td and donor-like shallow-gap states g_gd are major factors influencing the performance. g_ta is known to originate from the disorder of metal cation s-bands and the conduction band minimum mainly consists of In 5s orbitals. As a result, g_ta increases with the increase of In content, both g_td and g_gd are significantly affected by the oxygen vacancy. Since a Ga ion has a high ionic potential than In and Zn ions, it can combine the oxygen ions tightly. The formation of oxygen vacancies will be suppressed by the introduction of Ga. g_ta and g_td will decrease with the increase of Ga content. At last, the schematic of the proposed a-IGZO DOS model is shown in Fig. 1.

Fig.1 Proposed density of states (DOS) model for a-IGZO. EC and EV are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gta, gtd), while the dash curve near the conduction band edge represents the Gaussian-distributed donor-like oxygen vacancy (OV) states (ggd)

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The exponentially distributed band-tail states (g_ta, g_td), and the Gaussian-distributed donor-like OV states (g_gd) are represented as a function of energy by the following expressions:

(1) $$g_{\mathrm{ta}}(E)=n_{\mathrm{ta}}\exp [(E-E_C)/w_{\mathrm{ta}}],$$

(2) $$g_{\mathrm{td}}(E)=n_{\mathrm{td}}\exp [(E_V-E)/w_{\mathrm{td}}],$$

(3) $$g_{\mathrm{gd}}(E)=n_{\mathrm{gd}}\exp [-{(E-E_{\mathrm{gd}})}^{\mathrm{2}}/w_{\mathrm{gd}}^{\mathrm{2}}],$$

where E_C and E_V are conduction and valence band edge energies, n_ta and n_td are densities of states at E = E_C and E = E_V, respectively, w_ta and w_td are characteristic slopes of conduction and valence band-tail states, respectively. n_gd, E_gd and w_gd are the peak value, the mean energy, and standard deviation of states, respectively.

The device architecture we adopted in simulation is illustrated in Fig. 2.The TFT is simulated with a bottom-gate inverted staggered design, the active layer consists of two thin films with a cumulative thickness of 40 nm. The gate insulator layer we used is 80 nm thick thermal SiO₂, and the channel width/channel length (W/L) is 180 μm/30 μm.

Fig.2 Schematic of the TFT structure we adopt in this paper

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To model the device, the homogeneous Neumann boundary condition was applied to the back-channel surface of the a-IGZO layer2. Such boundary condition prevents carriers from flowing outside of the back-channel surface and ensures that the current only flows in/out of the device through source/drain (S/D) contacts during simulation. Since the degenerate conduction might occur in the a-IGZO TFT, the Fermi-Dirac statistic was used in the active layer simulation. Contacts between S/D electrodes and the a-IGZO layer were assigned as ohmic in this work. Both thermionic emission and tunneling current are considered.

Since the overlap between the s-orbital in multicomponent oxides affects the mobility and In content are more effective in s-orbital overlapping, the increase of the In content can increase the mobility [ 6].To date, a-IGZO has an electron band mobility ranging from 10 to 20 cm²/(V·s) in some researches [ 7− 12], and the electron band mobility of a-IZO (indium zinc oxide) can reach 59 cm²/(V·s) [ 13]. For high In content and negligible Ga content in layer1, we set the electron band mobility of layer1(In:Ga:Zn≈1:0:1 in atomic ratio) to 50 cm²/(V· s). And we set the electron band mobility of layer2 (In:Ga:Zn = 1:1:1 in atomic ratio) to 15 cm²/(V·s).

There are many different factors that influence the DOS of material, including the process conditions, the content of each constituent element, and so on. We focused on the influence of different constituent elements content on DOS in this work. We consider the fact that the DOS has a continuous distribution from tail states to extended states. Therefore, it is reasonable for N_C (effective conduction band DOS）(or N_V (effective valence band DOS)) and n_ta (or n_td) to have a proportional relation. Since N_C of a-IGZO (around 5 × 10¹⁸ cm⁻³) is about an order smaller than a-Si:H (around 3 × 10¹⁹ cm⁻³), we assumed n_ta of a-IGZO to be around 10²⁰ cm⁻³·eV⁻¹(n_ta for a-Si:H is 10²¹ cm⁻³·eV⁻¹) [ 8]. Since there are more In and less Ga in layer1 than layer2, and the DOS theory we mentioned above, the n_ta, n_td and n_gd of layer1 are higher than layer2. We set both the n_ta, n_td of layer1 to 2 × 10²⁰ cm⁻³·eV⁻¹ (n_ta, n_td of layer2 are both 1.55 × 10²⁰ cm⁻³·eV⁻¹). We set the n_gd of layer1 to 3 × 10¹⁷ cm^−3·eV⁻¹ (n_gd of layer2 is 6.5 × 10¹⁶ cm⁻³·eV⁻¹).

To calculate the electron affinity, we estimated χ_a-IGZO from a simple linear relation between electron affinities of its three elementary compounds [ 8]:

(4) $${\chi }_{a-IGZO}=a\ast {\chi }_{{In}_2{O}_3}+b\ast {\chi }_{{Ga}_2{O}_3}+c\ast {\chi }_{ZnO}$$

where a, b and c are molar percentages (mol %); ${\chi }_{{In}_2{O}_3}$ , ${\chi }_{{Ga}_2{O}_3}$ and ${\chi }_{ZnO}$ are 4.45, 3.19 and 4.5 eV, respectively. For layer2, In:Ga:Zn = 1:1:1 (a, b and c are 0.25, 0.25 and 0.5, respectively), _a-IGZO is calculated to be 4.16 eV. For layer1, the content of Ga is negligible, so In:Ga:Zn = 1:0:1 (a, b and c are 0.33, 0 and 0.67, respectively), χ_a-IGZO is calculated to be 4.48 eV.

The key simulation parameters in this study are summarized in Table 1.

Tab.1 Key simulation parameters of a-IGZO (based on Ref. [8])

symbol	layer1	layer2	unit	description
nta	2 × 1020	1.55 × 1020	cm−3·eV−1	density of tail states as E = EC
ntd	2 × 1020	1.55 × 1020	cm−3·eV−1	density of tail states as E = EV
wta	0.013	0.013	eV	conduction-band-tail slope
wtd	0.12	0.12	eV	valence-band-tail slope
ngd	3 × 1017	6.5 × 1016	cm−3·eV−1	peak of OV states
Egd	2.9	2.9	eV	mean energy of OV states
wgd	0.1	0.1	eV	standard deviation of OV states
χ	4.48	4.16	eV	electronic affinity
μn	50	15	cm2/(V·s)	band mobility (electron)
μp	0.1	0.1	cm2/(V·s)	band mobility (hole)
Eg	3.25	3.05	eV	bandgap

3 Results and discussion

We designed the IGZO-TFT with two active layers with different thickness, and different x (thickness of layer1) represent the variation of device thickness. Schematic of the TFT structure is shown in Fig. 2. Layer1 is the thin layer around the gate insulator, and layer2 is the back layer on the layer1. The active layer consists of these two layers with a cumulative thickness of 40 nm, x = 0 nm and x = 40 nm represent the TFT with 40 nm layer2 as active layer and the TFT with 40 nm layer1 as active layer respectively. We simulated each device, and the transfer characteristic curves are shown in Fig. 3.

Fig.3 Transfer characteristic curves of IGZO-TFT with different x (DL and SL represent double layers and single layer, respectively)

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Then, we analyzed the result with the “extract” function of atlas， which is based on the standard metal-oxide-semiconductor field-effect transistor (MOSFET) equation. The threshold voltage (V_th), sub-threshold swing (SS), on/off current ratio (I_ON/I_OFF), minimum drain current (I_Dmin) and maximum drain current (I_Dmax) are listed in Table 2.

Tab.2 Electrical properties of each a-IGZO TFT with different x

symbol	x of a-IGZO layer1/nm									unit
0	5	10	15	20	25	30	35	40
Vth	2.26	−0.41	−0.88	−0.89	−0.66	−0.23	0.36	1.16	1.72	V
SS	2.27	1.99	0.46	0.27	5.22	5.46	5.76	6.01	6.25	V/decade
ION/IOFF	2.22	2.2	17.5	69.8	14.5	1.37	0.02	10−9	10−9	1013
IDmin	2.96	7.27	0.74	0.18	0.99	12.12	955	1010	1010	10−19A
IDmax	6.51	16	13	12.9	14.3	16.6	19.1	21	22.1	10−6A

According to Table 2,when x = 40 nm (TFT with layer1 as active layer), the device has a maximum I_Dmax but a relatively bad performance in sub-threshold region because both mobility, density of tail states and donor-like states of layer1 are higher than layer2. On the contrary, the device has a minimum I_Dmax but a relatively good performance in sub-threshold region when x = 0 nm (TFT with layer2 as active layer).The I_Dmax of the other devices are between them, but the performances in sub-threshold region are better than them. The result is similar to other papers of TFT with double active layers [1−5].This is because that the TFT using high mobility material as front channel, the drain current is increased when the device is on. While with low mobility material as back channel, the drain current is decreased when the device is off.

Then, we considered the variation of threshold voltage, we found that, by introducing 5 nm layer1, the threshold voltage is suddenly changed from 2.26 V (x = 0 nm) to −0.41 (x = 5 nm). This is because that the main charge conductance channel is around the gate insulator interfaces [ 3], the 5 nm layer1 is either in this area or contains this area. As a result, the main charge conductance of x=5 nm device has a higher mobility and density of defect states than that of x=0 nm device , due to the high mobility and density of defect states, the channel region can be formed when low negative gate bias or no gate bias is applied. When x increases (ranging from x = 0 to 15 nm), the threshold voltage decreases (the absolute value is increased). We thought that the main charge conductance channels in this situation are layer1 and the interface region between layer1 and layer2 (since the interface between layer1 and layer2 is something like heterojunction, there is lattice mismatch between two layers, the dangling bonds will appear in the interface between two layers. That means interface trap density is introduced, and some carriers will accumulate in the interface [ 14]). Because of the increase in the thickness of layer1, the total density of defect states in the whole active layer are increased, the number of carriers in conductive areas is increased; a more negative gate bias is required to turn off the TFT by depleting the carriers from the conductive areas [ 5].The threshold voltage is increased with the increase in x (ranging from x=15 to 40 nm). We thought the main charge conductance channels in this situation are some part of layer1 near gate insulator and the interface region between layer1 and layer2; with the increase in the thickness of layer1, the interface between layer1 and layer2 is no longer near the gate insulator. The carriers only accumulate in the some part of layer1 near the gate insulator when positive gate voltage is applied, and relatively low negative gate bias (or even positive gate bias) is required to turn off the device.

On the other hand, the sub-threshold swing (SS) and on/off current ratio (I_ON/I_OFF) showed the same trend on x, the electrical performance improves when x increases from 0 to 15 nm, but declines when x increases from 15 to 40 nm. We thought that the electrical performance of device is determined by relative position between the main charge conductance channels (the active layer near the gate insulator) and the interface (between layer1 and layer2).

Further studies have been carried out on the influence of gate voltage on the distribution of carriers. We found similar characteristics of each device. For instance, we simulated the device of x = 10, 15 and 20 nm. The distribution of carriers in the whole active layer when −5 and 20 V gate voltages are applied respectively are illustrated as Figs. 4 and 5.

Fig.4 Carrier distribution of carriers when −5 V gate voltage is applied

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Fig.5 Carrier distribution of carriers when 20 V gate voltage is applied

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It can be seen from Figs. 4 and 5 that carriers will accumulate in the interface between two layers when negative gate voltage is applied. On the other hand, carriers will accumulate in the interface between two active layers and the areas of layer1 near gate insulator when positive gate voltage is applied

So we infer that the device with the interface (between layer1 and layer2) located in or near the main conductive channel has a low turn-on voltage because there already is large number of carriers in main conductive channel when positive gate voltage is applied. And it also has a good electrical performance as most of the carriers can get through the interface between layer1 and layer2 when negative gate voltage is applied; even when the carriers accumulate in the high resistive back active layer, the drain current that occurs is negligible, that means a low turn-off current. On contrary, the device with the interface (between layer1 and layer2) located far from the main conductive channel has a higher turn-on current because there are relatively more carriers ranging from the main conductive channel to the regions between layer1 and layer2, which have a low resistive. But when negative voltage is applied, most of the carriers may accumulate in the regions near the interface between layer1 and layer2, such regions have a relatively low resistive, so relatively large drain current will occur, that means a large turn-off current and poor electrical performance. By adjusting the thickness of layer1, we found a best device performance in x = 15 nm (V_th = −0.89 V, SS = 0.27, I_ON/I_OFF = 6.98 × 10¹⁴).

4 Conclusions

The thickness variation of each active layer in a-IGZO TFT with double layers and the interface between two active layers has been studied in this paper. It is found that the main conductive regions in double layer device are some active layer areas near gate insulator and the areas near the interface between two active layers. When negative voltage is applied, most of the carriers will accumulate in the interface between two active layers. On the other hand, most of the carriers will accumulate in the interface between two active layers and the areas of layer1 near gate insulator when positive gate voltage is applied. The electrical performance of device changes with the changing location of the interface between two active layers and we found the best performance of V_th = −0.89 V, SS = 0.27, I_ON/I_OFF = 6.98 × 10¹⁴ when x = 15 nm.

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Acknowledgements

This work was financially supported by a fund for professor cultivation project of Nanning University (No. 2014JSGC01). The author would like to thank facility support of the Center for Nanoscale Characterization and Devices (CNCD), WNLO-HUST and the Analysis and Testing Center of Huazhong University of Science and Technology.

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2016 Higher Education Press and Springer-Verlag Berlin Heidelberg