Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

{{article.zuoZheEn}}

PDF(548 KB)
PDF(548 KB)
Front. Optoelectron. ›› 2013, Vol. 6 ›› Issue (3) : 327-337. DOI: 10.1007/s12200-013-0328-8
RESEARCH ARTICLE

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

  • {{article.zuoZheEn}}
Author information +
History +

Highlights

{{article.highlightEn}}

Abstract

{{article.abstractEn}}

Author summary

{{article.authorSummayEn}}

Keywords

Cite this article

EndNote

Ris (Procite)

Bibtex

Download citation ▾
{{article.zuoZheEn_L}}. {{article.titleEn}}. Front Optoelec, 2013, 6(3): 327‒337 https://doi.org/10.1007/s12200-013-0328-8

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

RIGHTS & PERMISSIONS

{{article.copyright.year}} {{article.copyright.holder}}
Share on Mendeley
PDF(548 KB)

Accesses

Citations

Detail
Sections
Recommended

/

〈 〉