Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Bipin Kumar VERMA, Shyam Babu SINGH, Shyam AKASHE

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PDF(548 KB)
Front. Optoelectron. ›› 2013, Vol. 6 ›› Issue (3) : 327-337. DOI: 10.1007/s12200-013-0328-8
RESEARCH ARTICLE
RESEARCH ARTICLE

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

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Abstract

Multi-threshold complementary metal-oxide-semiconductor (MTCMOS) is often used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode (sleep-to-active) is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45 nm CMOS technology.

Keywords

multi-threshold complementary metal-oxide-semiconductor (MTCMOS) / mode transition / ground bounce noise / sleep transistor

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Bipin Kumar VERMA, Shyam Babu SINGH, Shyam AKASHE. Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier. Front Optoelec, 2013, 6(3): 327‒337 https://doi.org/10.1007/s12200-013-0328-8

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Acknowledgements

This work was supported by ITM University Gwalior, with collaboration Cadence Design System, Bangalore.

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2014 Higher Education Press and Springer-Verlag Berlin Heidelberg
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