Analysis of TiO₂ for microelectronic applications: effect of deposition methods on their electrical properties

Abstract

Metal oxide semiconductor (MOS) device down-scaling is a powerful driving force for the evolution of microelectronics. The downsizing rate of metal oxide semiconductor field effect transistors (MOSFETs) is really marvelous. Silicon dioxide (SiO₂) has served as a perfect gate dielectric for the last four decades. Due to physical limitations, leakage current, high interface trap charge it now needs to be replaced with higher permittivity dielectric material. Keeping the motivation for the search of high-k materials, extensive studies have been carried out on several metal oxides, such as ZrO₂, Ta₂O₅, TiO₂, Al₂O₃ and HfO₂ for the replacement of SiO₂. The high dielectric constant (k) of titanium dioxide (TiO₂) will open multifaceted prospects for the use of this material in microelectronic devices. In this paper, a comparative study of various deposition methods for fabrication of thin TiO₂ films has been presented. This work uses a combination of simulation results, experimental data and critical analysis of published data. Further, an experiment using sol-gel method has been carried out to deposit thin films of TiO₂. It has been characterized and compared with the earlier reported fabrication methods. The X-ray diffraction analyses and Raman spectra indicate the presence of anatase TiO₂ phase in the film. The dielectric constant as calculated using capacitance-voltage (C-V) analysis was found to be 23. The refractive index of the film was 2.43. The TiO₂ films studied for microelectronic applications and present acceptable properties such as low leakage current density of 1.0×10^-5 A/cm at 1 V and band gap of 3.6 eV. The leakage current has been found to be dominant by the Schottky emission at lower electric field, while Flower-Nordheim (F-N) tunneling occurs at higher biasing voltages.

Keywords

titanium dioxide (TiO₂) / high-k material / sol-gel / thin films / atomic force microscopy (AFM) / capacitance-voltage (C-V) analysis

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Acknowledgements

The author would like to thanks Assistant Professor, Dr. Savita Rathee from Department of Mathematics, Maharshi Dayanand University Rohtak, India, for her cooperation and regular guidance. The author also wants to thank Mr Naveen Goel, H.O.D M. Tech, Department of Electronics & Communications, Vaish College College of Engineering, Rohtak, India for his many insightful discussions.

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