Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

Abstract

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al₂O₃ were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD) techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.

Keywords

high-k tunnel oxide / equivalent oxide thickness (EOT) / charge trapping memory (CTM) prototype / atomic layer deposition (ALD) technique / multi-level cell (MLC) storage

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Acknowlegements

This work was partly supported by the National Natural Science Foundation of China (Grant Nos. 61076005, 60706019, 60928009, and 61076017), the Natural Science Foundation of Jiangsu (No. BK2008025), and the National Key Scientific Program – Nanoscience and Nanotechnology Project (No. 2006CB0L1000).

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2014 Higher Education Press and Springer-Verlag Berlin Heidelberg