Erasure codes are being widely implemented in distributed storage systems to achieve fault tolerance with high storage efficiency. Reed-Solomon code is commonly deployed in data centers due to its optimal storage efficiency, but it requires massive bandwidth for node repair. Minimum Storage Regenerating code (MSR) and Locally Repairable (LR) code are proposed to reduce repair bandwidth, which is defined as the amount of data communicated during node repair. However, MSR code usually carries a heavy disk I/O burden and LR code is not optimal in storage efficiency. In this paper, we take disk I/O, storage efficiency, repair bandwidth and sub-packetization level into consideration together, and propose novel constructions of maximum distance separable array codes with low disk I/O, reduced repair bandwidth and very small sub-packetization level of . We focus on the repair of systematic nodes since they are more likely to fail than parity nodes. Specifically, the proposed codes achieve the cut-set bound on repair bandwidth for systematic nodes when the code rate , and for , the repair bandwidth is less than twice of the cut-set bound. Compared with new advanced piggybacking codes, the proposed codes obtain a significant reduction on repair bandwidth for systematic nodes while also consuming less disk I/Os. In terms of average repair bandwidth of all nodes, the proposed codes are intuitively better than the existing advanced piggybacking codes.
Workload identification is fundamental for resource management in stream computing systems and is a key factor in improving their cost-benefit. However, existing workload identification algorithms often fail to handle the diversity of workload types and the complexity of the environments, making them usually unable to provide guidance for improving the performance of stream computing systems.
In this work, we propose two workload identification algorithms for different scenarios. The first one is the Fine-Grained I/O traces Workload Identification (FGWI) algorithm, which is suitable for the system that is not sensitive to overhead but mostly pursues the identification F1-score. FGWI analyzes the basic, time, spatial and temporal access features of every I/O operation, and then utilizes CatBoost to classify the workloads, meeting the high F1-score requirement. The second one is the simplified version of FGWI called AWI (Aggregated I/O traces Workload Identification), which mostly focuses on the temporal accesses features of minute-level aggregated I/O traces to reduce the overhead. We conduct experiments driven by the traces collected from Alibaba Cloud to evaluate the two algorithms. Experimental results demonstrate that, FGWI achieves an average 8.2% improvement in F1-score compared to the state-of-the-art algorithms, while AWI maintains a time overhead of only 0.22% relative to FGWI, but achieving an average of 6.8% improvement in F1-score compared to the state-of-the-art algorithms. Both algorithms present robustness and scalability across disks, proving their effectiveness for workload identification.
The performance of current computer system is limited by the Memory Wall caused by the unbalanced development between memory technology and processor technology. To reduce the overhead of data movement between memory and processor, a series of Processing-in-Memory (PIM) systems have been developed to move computing closer to memory. In this article, PIM focuses on exploiting the analog operational properties to compute in DRAM. We provide a comprehensive summary from three perspectives: the development of PIM’s basic operations, the programmability of PIM and the challenges faced by PIM. The development of PIM’s basic operations focuses on current development in implementing various types of computation, such as logic operations and complex arithmetic operations. The programmability of PIM emphasizes the combination of PIM systems with existing systems and the development of ISAs, libraries and compiler systems to enhance ease of programming. The challenges faced by PIM primarily highlight some crucial obstacles in terms of software and architecture development. Current developments of PIM present both opportunities and challenges, and the goal of this article is to provide researchers with a comprehensive understanding of PIM’s advancements.
The rapid expansion of the Internet of Things (IoT) has led various IoT manufacturers to independently incorporate their platform management stack as a Device Management Channel (DMC) into IoT devices, resulting in a heterogeneous and disjointed IoT ecosystem. This decentralization poses significant challenges in access control security for managing IoT devices through standalone DMCs. The introduction of new market demands, such as device sharing and multiple attribute management, exacerbates vulnerabilities in IoT devices, leading to Chaotic Device Management (Codema). Existing access control systems prove insufficient for handling multiple DMC scenarios and lack fine-grained attribute management capabilities. This paper conducts an analysis of the overlooked manufacturer local DMC, identifying new vulnerabilities across DMCs. To tackle the security challenges associated with managing multiple DMCs, we propose MDUCON, a formal fine-grained access control model. Additionally, we introduce DMCGuard, a cross-DMC authorization management framework designed for seamless integration into IoT devices by vendors, enhancing authorized management of multiple DMCs on IoT devices. DMCGuard undergoes deployment on four mainstream DMCs, aligning with the prevailing structure of IoT systems. The evaluation demonstrates the robust security and effectiveness of DMCGuard in real-world IoT scenarios, affirming its potential to address DMC security challenges.
Serverless computing usually employs secure containers, which are encapsulated within lightweight microVMs, to isolate function invocations across different tenants. For high security guarantees, such Single-Container-Per-VM (SCPV) model results in large memory waste, as each microVM includes a guestOS, even though they are identical. For memory efficiency of the secure container architecture, we advocate for the dynamic Multi-Containers-Per-VM (MCPV) model. Adopting the MCPV model, a microVM can accommodate multiple containers for the same functions, and the microVM’s memory space adjusts dynamically based on workload.
However, implementing this model necessitates efficient memory hot-plug and hot-unplug techniques. Existing methods either significantly impair function performance within containers or fail to adequately unplug all required pages. To address this challenge, we propose CZone, a dedicated memory hot-plug and hot-unplug design specifically tailored to support the dynamic MCPV model. CZone ensures that the used memory pages of a container are located in contiguous physical memory regions, with each region exclusively allocated to a single container. Experimental results demonstrate that MCPV with CZone brings an 81.81% reduction in startup latency and an 89.87% reduction in memory footprint when compared to the existing SCPV model that utilizes microVM templating, with negligible system performance impact.
Traditional server-based data centers suffer from low resource utilization, insufficient hardware scalability, insufficient resource usage elasticity, and low fault tolerance. With the ever-increasing network speed and processing power in hardware controllers, physically disaggregating the coupled resources in a server has been a promising trend for building next-generation data centers, as it effectively addresses the limitations of server-based data centers. Although some existing works follow this trend, how to build an efficient physically resource-disaggregated data center (PRD-DC) is still in the exploring stage. Thus, in this article, we first describe the trends and technique routes for PRD-DCs. Then, we present a potential solution for realizing a PRD-DC, named Serverless DC, including the I/O Processing Unit (IPU), SDC-kernel, and networking systems for controlling, managing, and connecting disaggregated storage/computing units respectively. Finally, some open research issues in PRD-DC are discussed.
Apache Spark is one of the most popular in-memory distributed computing frameworks for processing large-scale datasets, and caching is indispensable for improving the performance of different Spark applications. However, proper cache usage in Spark is non-trivial. Developers must cache the hot data manually and evict unnecessary data timely in their applications to achieve better performance. This requires deep understanding and sufficient experience. Otherwise, the wrong caching decisions can lead to performance degradation, application bugs, and even system crashes. To overcome these challenges, we propose AutoCache, in a non-intrusive manner, which means it can identify the hot datasets and cache them automatically during the execution of a workload without changing any application code. For a given Spark application, AutoCache first parses the execution paths of the application and then analyzes the data references based on the DAG maintained within Spark. After that, AutoCache heuristically identifies the datasets, in the form of RDDs, that would be accessed multiple times at run time. Along with the application’s execution, AutoCache automatically caches and evicts the RDDs by invoking Spark’s underlying APIs on the fly. We evaluate AutoCache by using an open-source benchmark that contains various applications. Our experimental results show that AutoCache can significantly improve the performance of real-world applications and obviously outperform related work. Moreover, by comparing the caching decisions of AutoCache with existing manual written caching logics in these applications, nine previously unknown caching-related issues are detected, all of them have been confirmed and five of them have been fixed by related developers. This constructs another strong proof of the effectiveness of AutoCache.
In the era of the knowledge economy, understanding how job skills influence salary is crucial for promoting recruitment with competitive salary systems and aligned salary expectations. Despite efforts on salary prediction based on job positions and talent demographics, there still lacks methods to effectively discern the set-structured skills’ intricate composition effect on job salary. While recent advances in neural networks have significantly improved accurate set-based quantitative modeling, their lack of explainability hinders obtaining insights into the skills’ composition effects. Indeed, model explanation for set data is challenging due to the combinatorial nature, rich semantics, and unique format. To this end, in this paper, we propose a novel intrinsically explainable set-based neural prototyping approach, namely LGDESetNet, for explainable salary prediction that can reveal disentangled skill sets that impact salary from both local and global perspectives. Specifically, we propose a skill graph-enhanced disentangled discrete subset selection layer to identify multi-faceted influential input subsets with varied semantics. Furthermore, we propose a set-oriented prototype learning method to extract globally influential prototypical sets. The resulting output is transparently derived from the semantic interplay between these input subsets and global prototypes. Extensive experiments on four real-world datasets demonstrate that our method achieves superior performance than state-of-the-art baselines in salary prediction while providing explainable insights into salary-influencing patterns.
High-performance data center network infrastructure and hardware equipment are rapidly evolving to provide a high-quality platform for increasingly complex and diverse cloud applications. However, relying solely on equipment upgrades cannot fully alleviate the challenges posed by rapidly changing internal traffic patterns. Efficient collaboration among congestion control, load balancing, flow scheduling, and other technologies is essential to enhance the network traffic transmission performance of data centers. We analyze the challenges in data center network congestion control. We reclassify congestion control protocols from a temporal and spatial perspective and proposed a classification method, named data and credit and end-to-end feedback (DCEF) congestion control framework. We describe the features under each category and summarize them. We also compare the differences in performance, convergence, deployment, and other aspects of some representative congestion control protocols. Finally, we look forward to the future development of congestion control.