AdaptiveDSE: Gradient-Driven Adaptive Guidance for Chiplet-Based AI Accelerator Architecture Design Space Exploration

Abstract

While chiplet technology addresses the scaling bottlenecks of traditional Systems-on-Chip (SoCs), its heterogeneous nature introduces an explosively large design space. Confronted with such a vast design space, architecture design space exploration (DSE) is necessary. By performing early-stage screening of design configurations, DSE avoids expensive redesigns later in the development flow. However, current DSE methods face a dilemma in balancing efficiency with generality. The pursuit of efficiency is often tightly coupled to specific design spaces. Conversely, the pursuit of generality lacks guidance, resulting in low exploration efficiency.

To this end, we present AdaptiveDSE, a DSE framework with high efficiency and sufficient generality. The core principle of AdaptiveDSE lies in the utilization of gradient information. By leveraging gradients, the algorithm is able to explicitly capture the intrinsic relationship between design parameters and exploration directions. Based on this guiding relationship, AdaptiveDSE not only provides clear guidance for the exploration process but also dynamically captures such guidance during the process. Compared with state-of-the-art (SOTA) Chiplet-Gym, which includes SA and RL methods, AdaptiveDSE demonstrates high efficiency and excellent generality. AdaptiveDSE achieved an 18.91%improvement in Performance, Power, and Cost (PPC) compared to SA. Compared with RL, AdaptiveDSE not only increased the PPC by 4.84%, but also significantly reduced the running time to 3.25% of that of RL. Additionally, AdaptiveDSE not only reduces the standard deviation by 86.38% and 95.06% over SA and RL, respectively, but also requires no retraining when exploring different design spaces.

Keywords

chiplet / electronic design automation / design space exploration / gradient

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Higher Education Press 2026

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