ECOSight: an explainable graph AI tool for automated decision-making in timing ECO

Huiqing YOU; Xiaowei HE; Wencheng JIANG; Bo HU; Peiyun BIAN; Zexiang CHENG; Chaochao FENG; Daheng LE; Pengcheng HUANG; Chiyuan MA; Zhenyu ZHAO

doi:10.1007/s11704-026-51891-6

Front. Comput. Sci. ›› 2027, Vol. 21 ›› Issue (7) :2107207 DOI: 10.1007/s11704-026-51891-6

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ECOSight: an explainable graph AI tool for automated decision-making in timing ECO

Huiqing YOU ¹^,²^,^‡
, Xiaowei HE ¹^,²^,^‡
, Wencheng JIANG ¹^,²
, Bo HU ¹^,²
, Peiyun BIAN ¹^,²
, Zexiang CHENG ¹^,²
, Chaochao FENG ¹^,²
, Daheng LE ¹^,²
, Pengcheng HUANG ¹^,²
, Chiyuan MA ¹^,²
, Zhenyu ZHAO ¹^,²

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Huiqing YOU, Xiaowei HE, Wencheng JIANG, Bo HU, Peiyun BIAN, Zexiang CHENG, Chaochao FENG, Daheng LE, Pengcheng HUANG, Chiyuan MA, Zhenyu ZHAO. ECOSight: an explainable graph AI tool for automated decision-making in timing ECO. Front. Comput. Sci., 2027, 21 (7) : 2107207 DOI:10.1007/s11704-026-51891-6

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References

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[1]	Yang T, Zhao Z, Han A, Liu G. Automatic timing eco using stage-based path delay prediction. In: Proceedings of the 20th IEEE Interregional NEWCAS Conference (NEWCAS). 2022, 455–459

[2]	He X, Fu Z, Wang Y, Liu C, Guo Y. Accurate timing prediction at placement stage with look-ahead RC network. In: Proceedings of the 59th ACM/IEEE Design Automation Conference. 2022, 1213–1218

[3]	Shrestha P, Phatharodom S, Savidis I. Graph representation learning for gate arrival time prediction. In: Proceedings of the 4th ACM/IEEE Workshop on Machine Learning for CAD. 2022, 127–133

[4]	Alrahis L, Knechtel J, Klemme F, Amrouch H, Sinanoglu O . GNN4REL: graph neural networks for predicting circuit reliability degradation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41( 11): 3826–3837

[5]	Guo Z, Liu M, Gu J, Zhang S, Pan D Z, Lin Y. A timing engine inspired graph neural network model for pre-routing slack prediction. In: Proceedings of the 59th ACM/IEEE Design Automation Conference. 2022, 1207–1212

[6]	Jiang W, Zhao Z, Luo Z, Zhou J, Zhang S, Hu B, Bian P . TSTL-GNN: graph-based two-stage transfer learning for timing engineering change order analysis acceleration. Electronics, 2024, 13( 15): 2897

[7]	Lu Y C, Nath S, Khandelwal V, Lim S K. RL-Sizer: VLSI gate sizing for timing optimization using deep reinforcement learning. In: Proceedings of the 58th ACM/IEEE Design Automation Conference (DAC). 2021, 733–738

[8]	Jiang W, Chhabria V A, Sapatnekar S S. IR-aware ECO timing optimization using reinforcement learning. In: Proceedings of 2024 ACM/IEEE International Symposium on Machine Learning for CAD. 2024, 7

[9]	Zhou X, Ye J, Pui C W, Shao K, Zhang G, Wang B, Hao J, Chen G, Heng P A. Heterogeneous graph neural network-based imitation learning for gate sizing acceleration. In: Proceedings of the 41st IEEE/ACM International Conference on Computer. 2022, 1–9

[10]	Lu Y C, Kunal K, Pradipta G, Liang R, Gandikota R, Ren H. LEGO-Size: LLM-enhanced GPU-optimized signoff-accurate differentiable VLSI gate sizing in advanced nodes. In: Proceedings of 2025 International Symposium on Physical Design. 2025, 152–162