Single polarization photonic crystal fiber filter based on surface plasmon resonance

Abstract

In this paper, we propose a photonic crystal fiber (PCF) polarization filter based on surface plasmon resonance (SPR) characteristics. Gold nanowire is used as the active plasmonic material. Light into silica core becomes coupled to gold nanowire stimulating SPR. It splits light into two orthogonal (x-polarization and y-polarization) polarization in the second order of surface plasmon polarization. Numerical investigations of the proposed PCF filter is finite element method (FEM). By tuning the diameter of gold nanowire and shifting their position, the performance of the proposed PCF filter is inspected rigorously. Filtering of any polarization can be obtained by properly placing the metal wires. The maximum confinement loss of x-polarization is 692.25 dB/cm and y-polarization is 1.13 dB/cm offers at resonance position 1.42 µm. Such a confinement loss difference between two orthogonal polarizations makes PCF a talented candidate to filter devices. Consequently, the recommended PCF structure is useful for polarization device.

Keywords

photonic crystal fiber (PCF) / surface plasmon resonance (SPR) / perfectly match layer / polarization filter

1 Introduction

In today’s semiconductor device industries, it has been challenged to develop high performance portable systems with reliability in data transmission. Metal-oxide-semiconductor field-effect transistor (MOSFET) scaling deep into sub-100 nm regime leads to shrink operating voltage, and causes larger leakage current and ground bounce noise [1]. In resent year, leakage current and ground bounce noise have been considered as critical design parameters in wireless communication systems [2,3].

Multi-threshold complementary metal-oxide-semiconductor (MTCMOS) is commonly used technique for leakage current suppression [4,5]. In MTCMOS circuit, high threshold voltage (high-V_TH) sleep transistors are used at header and footer of the circuit. It is used to cutoff the power supply and ground connection of the idle low threshold voltage (low-V_TH) circuit blocks [6]. These sleep transistors are either high-V_TH p-type metal-oxide-semiconductor (pMOS) transistor or a high-V_TH n-type metal-oxide-semiconductor (nMOS) transistor. A high-V_TH pMOS sleep transistor is attached between a real power line (power supply) and a virtual power line (low-V_TH circuit blocks), as shown in Fig. 1. Alternatively, a high-V_TH nMOS sleep transistor is connected between actual ground and virtual ground (low-V_TH circuit blocks). These sleep transistors at header and footer are turned off to reduce the sub-threshold leakage current in idle circuits.

Fig.1 Power and ground bounce noise generated in conventional MTCMOS technique on multiplier circuit

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When the circuit is transited from Sleep-to-Active mode, ground bounce noise is occurring due to the large voltage fluctuation on both real power line and real ground line, as shown in Fig. 1. In this paper, ground bounce noise in MTCMOS circuit with multiplier is evaluated. Multipliers are the fundamental and essential building blocks of very-large-scale-integration (VLSI) systems, microprocessor (µP), digital signal processing (DSP), etc. The profile growth in semiconductor device industry has led to the development of high performance portable systems with low power modules [7]. Multiplier has three input sequences: parallel, serial and hybrid (parallel-serial) approach. Parallel approach multiplier has higher speed and better performance [8,9]. The operation of parallel multiplier can be divided into two parts: 1) formation of the partial products, and 2) summation of these partial products to form final products, as shown in Fig. 2.

Fig.2 Basic operation of multiplier

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The multiplier is a complex adder array structure. The performance and characteristics of multiplier depend on the algorithm, in which they are operated [7]. Bit array multiplier has regular and simple structure. Figure 3 shows block diagram of 4 × 4 bit-array multiplier. The partial product is generated by multiplying, multiplicand and multiplier bits [8]. The partial products are shifted to their bit orders and then added by adders. If there are N numbers of partial products in multiplier, then (N-1) bit adders are required. The paper is organized as follows: different noise aware MTCMOS techniques introduced in Section 2; simulation and results are explained in Section 3; this paper is concluded in Section 4.

Fig.3 Design of 4 × 4 bit-array multiplier (HA=half adder, FA=full adder)

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2 Noise aware MTCMOS techniques

In this section, different noise-aware MTCMOS techniques are presented. Tri-mode MTCMOS circuit techniques are presented in Section 2.1. Dual-switch MTCMOS technique is shown in Section 2.2. Tri-transistor-controlled MTCMOS circuit technique is introduced in Section 2.3.

2.1 Tri-mode MTCMOS technique

In this section, we designed our circuit with Tri-mode MTCMOS technique [10]. An additional intermediate park (wait) mode is introduced between mode transitions (sleep-to-active). A high-V_TH pMOS transistor is attached in parallel with high-V_TH nMOS transistor in the footer of the circuit, as shown in Fig. 4.

Fig.4 Tri-mode MTCMOS technique [10].

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In standby mode, both N₁ and park transistor are turned off to reduce the sub-threshold leakage current. In sleep mode, the voltage at virtual ground (GND/VGnd1) is maintained at ~V_DD (supply voltage). The mode transitions are divided into two parts, such as sleep-to-park mode and park-to-active mode transition. In sleep-to-park mode transition, the park transistor is turned on while N₁ is maintaining cutoff. The virtual ground line voltage is discharged through the P1 transistor [parker (V_TP)]. The ground bounce noise is suppressed due to lower voltage swings on the virtual ground in park mode transition, as shown in Fig. 4. In park-to-active mode transition, the footer transistor N₁ is turned on and the park transistor is turned off. In active mode, the virtual ground voltage discharges up to ~V_DD.

2.2 Dual-switch MTCMOS technique

In this section, we designed a circuit with dual-switch MTCMOS technique [10,11]. A high-V_TH nMOS transistor (N₂) is connected parallel to header sleep transistor (P₁) between virtual V_DD and real V_DD. Similarly, a high-V_TH pMOS transistor (P₂) is connected parallel to footer sleep transistor (N₁) between virtual ground and real ground line, as shown in Fig. 5. An intermediate hold mode is introduced with the help of extra transistors.

Fig.5 Dual-switch MTCMOS technique [11]. High-VTH sleep transistors are represented by thick channel length. 0 V<VMIN<VDD

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In sleep mode, transistors P₁, N₁, P₂ and N₂ are turned off to reduce the sub-threshold leakage current. The voltages at virtual power (V_DD) and virtual GND are approximately equalized (VMID). In first transition (sleep-to-hold) mode, transistors P₂ and N₂ are turned on, and transistors P₁ and N₁ are turned off. A differential voltage of V_DD-VMIN-V_TN is produced at virtual V_DD, and VMIN-V_TP is produced at virtual GND. In second transition (hold-to-active) mode, transistors P₁ and N₁ are later activated. In active mode, the virtual power line is discharging up to ~V_DD and virtual ground line is discharging up to ~V_GND. The ground bounce noise is alleviated by reducing voltage fluctuation on virtual lines during transition from sleep mode to active mode through hold mode, as shown in Fig. 5.

2.3 Tri-transistor-controlled MTCMOS technique

In this section, we designed our circuit with Tri-transistor-controlled MTCMOS technique [12] to suppress the ground bounce noise in sleep-to-active mode transition. A high-V_TH pMOS transistor is connected parallel to footer for introducing a doze mode in MTCMOS circuit, as shown in Fig. 6(a).

Fig.6 Tri-transistor-controlled MTCMOS circuit. (a) TTH; (b) TTL [12]. High-VTH sleep transistors are represented by thick channel length. 0 V<VMIN<VDD

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In sleep mode, the sleep transistors (header and footer) and doze transistor are turned off to reduce the sub-threshold leakage current. In sleep mode, the virtual GND voltage is ~VMIN. The sleep-to-active mode transition is divided into sleep-to-doze mode and doze-to-active mode. In sleep-to-doze mode, the header and doze transistors are turned on and footer transistor is turned off. The virtual GND voltage is discharged up-to the threshold voltage of doze transistor (V_TP). In doze-to-active mode transition, the header and footer transistors are turned on and doze transistor is turned off. The virtual GND voltage is discharged from V_TP to ~V_GND. By reducing the voltage fluctuation, on virtual GND, we reduced the ground bounce noise in each mode transition with two-step wake-up process. To reduce transition delay from sleep-to-doze mode, a low-V_TH doze transistor is used, as shown in Fig. 6(b). Tri-transistor-controlled MTCMOS technique (high-V_TH doze transistor (TTH) and low-V_TH doze transistor (TTL)) is evaluated in this section.

3 Simulation and results

In this section, we simulated our low power multiplier with following techniques: tri-mode MTCMOS [10], dual-switch MTCMOS [11] and tri-transistor-controlled MTCMOS [12]. In this paper, we characterized on ground bounce noise, leakage current and active power consumption.

3.1 Ground bounce noise

In this section, we analyzed ground bounce noise on transistor sizes, temperature and voltage scaling for different MTCMOS techniques. The commonly used 40-pin dual-in-line package (DIP-40) model is used to calculate the ground bounce noise for different MTCMOS circuit techniques [13,14]. The basic model of DIP-40 model is shown in Fig. 7.

Fig.7 DIP-40 package pin ground bounce noise model

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3.1.1 Effect of voltage scaling on ground bounce noise

In this section, the dependence of ground bounce noise on the voltage was evaluated. The peak of ground bounce noise with tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) circuit for various voltages is shown in Table 1.

Tab.1 Effect of voltage scaling on ground bounce noise (unit: mV)

				voltages
	0.7 V			0.9 V			1 V
transistor size /nm	2.67	10	15	2.67	10	15	2.67	10	15
conventional	2.149			4.156			3.511
tri-mode	0.122	0.125	0.127	1.299	1.3	1.286	2.616	2.593	2.51
dual switch	0.117	0.115	0.115	0.883	0.876	0.890	1.628	1.62	1.603
TTH	0.115	0.113	0.112	0.879	0.892	0.895	1.629	1.614	1.624
TTL	0.112	0.111	0.110	0.874	0.905	0.901	1.625	1.617	1.614

As shown in Fig. 8, tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) circuits reduce the ground bounce noise by 68%, 78.74%, 78.82% and 78.94% respectively compared to conventional circuit.

The intensity of ground bounce noise is dependent on the rate of change of the instantaneous current (dI/dt) conducted by sleep transistor during sleep-to-active mode transition [15]. The peak amplitude of ground bounce noise is directly proportional to supply voltage. If we increase the supply voltage of circuit, ground bounce noise will also increase. When higher supply voltage is applied, then voltage fluctuation on virtual line increases and the ground bounce noise also increases. Figure 9 shows the effect of ground bounce noise with different circuit techniques on multiplier. In Fig. 9(a), it is clear that the ground bounce noise is produced by the voltage fluctuation. Due to voltage fluctuation, the peak amplitude of ground bounce noise is varies every time. When the ground bounce noise reduction technique are used, the voltage fluctuation at virtual ground is reduced which reduced the peak amplitude of ground bounce noise, as shown in Figs. 9(b), 9(c), 9(d) and 9(e).

Fig.8 Percentage ground bounces noise reduction provided by different MTCMOS circuit techniques as compared to conventional circuit.

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Fig.9 Waveform showing ground bounce noise at real ground (0.9 V and W/L = 2.67 nm). (a) Conventional design; (b) tri-mode design; (c) dual-switch design; (d) TTH; (e) TTL

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3.1.2 Effect of transistor size on ground bounce noise

The ground bounce noises with different size of the controlling transistor (park for tri-mode, dual-switch for dual-switch circuits and dozer for tri-transistor-controlled (TTH and TTL) circuits) were evaluated in this section. The different sizes of transistor are determining the charging and discharging speed during the transition from sleep-to-intermediate mode (park, hold and doze). The effect of dozer size on ground bounce noise was evaluated. The waveform of virtual ground line voltage and real ground line voltage is shown in Figs. 10 and 11, respectively.

Fig.10 Waveform of virtual ground line voltage of TTH circuit during transitions from sleep-to-active mode through doze mode. The duration of doze mode is 87.41 ns. (a) Virtual ground line voltage with small doze (dozersmall = 2.67 nm); (b) virtual ground line voltage with larger doze (dozerlarge = 15 nm)

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When the size of dozer is small, the virtual GND line voltages discharge slowly during sleep-to-doze mode transition. Hence, it reduces the rate of change of the instantaneous current. In steady-state doze mode, virtual ground line voltage is higher with a smaller dozer, the voltage fluctuation on virtual ground line in sleep-to-doze mode is narrower. At higher steady-state doze mode, virtual ground line voltage has higher fluctuation at virtual ground line during doze-to-active mode transition. The relaxation time for the different circuit techniques are shown in Table 2.

Tab.2 Relaxation time for different circuits (unit: ns)

	transistor size
	2.67 nm	10 nm	15 nm	20 nm
tri–mode	88.56	20.51	52.45	64.57
dual–switch	133.82	37.53	28.47	27.68
TTH	87.41	22.98	25.32	39.45
TTL	79.66	25.67	30.74	38.46

When the dozer size is larger, the virtual ground line voltages discharge faster during sleep-to-doze mode transition. In steady-state doze mode, the voltage fluctuation at virtual ground line is increased. Alternatively, during doze-to-active mode transition, the voltage fluctuation on virtual ground line is reduced with larger dozer, as shown in Fig. 10.

Fig.11 Waveform of real ground voltage of TTH circuit during transitions from the sleep-to-active mode through doze mode. The duration of doze mode is 87.41 ns. (a) Ground bounce noise on real ground with smaller doze (dozersmaller = 2.67 nm). (b) ground bounce noise on real ground with larger doze (dozerlarge = 15 nm)

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As shown in Table 3, if we increase the size of the controlling transistor, then it affects the ground bounce noise of the circuit. Tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) MTCMOS circuit reduced the ground bounce noise by 68.74%, 78.75%, 78.84% and 78.97% respectively compared to conventional circuits.

Tab.3 Effect of transistor size on ground bounce noise (unit: mV)

	transistor size
	2.67 nm	10 nm	15 nm	20 nm
conventional	4.156
tri-mode	1.299	1.3	1.286	1.265
dual-switch	0.883	0.876	0.890	0.883
TTH	0.879	0.892	0.895	0.893
TTL	0.874	0.905	0.901	0.899

3.1.3 Effect of temperature on ground bounce noise

In this section, the dependence of ground bounce noise on temperature was studied. The peak of ground bounce noise with tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) circuit for 27°C, 70°C and 110°C are shown in Fig. 12.

Fig.12 Peak amplitude of ground bounces noise for tri-mode, dual-switch, TTH and TTL at different temperatures

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At higher temperature, the saturation current of sleep transistor is decreased because of reduction in carrier mobility [16]. A smaller size sleep transistor current trends to lower the peak amplitude of the ground bounce noise when these sleep transistors are activated. However, the virtual ground line voltage is changed with the voltage fluctuation. The effective resistance of the parker and dozer are increased with higher temperature. In the steady-state intermediate mode, virtual ground line voltage is increased with higher temperature. The range of virtual ground line voltage increased during the transition from intermediate-to-active mode. Therefore, there are tends that the peak ground bounce noise of tri-mode, dual-switch and tri-transistor-controlled circuit increases with higher temperature.

The increased in steady-state virtual ground line voltage and the reduction in saturation current of sleep transistor have opposite effect on peak ground bounce noise with higher temperature. The variation of ground bounce noise on temperature with transistor size is shown in Fig. 12. Due to opposite effect of steady-state virtual ground line voltage and saturation current, the ground bounce noise is weaker dependence on temperature. The tri–mode, dual-switch and tri–transistor–controlled (TTH and TTL) circuit reduced the ground bounce noise by 41%, 59.93%, 60.09% and 60.32% respectively compared to conventional circuit.

3.2 Leakage current

The leakage current of multiplier with tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) techniques was evaluated in this section. The size of parker in tri-mode, dozer in tri-transistor-controlled and dual–switch in dual–switch circuits is minimum (W/L = 2.67 nm). The leakage current of different circuits are shown in Table 4. The sub-threshold leakage current is produced by high-V_TH sleep transistors in MTCMOS circuit. The gate tunneling currents are primary leakage, produced by low-V_TH transistors of logic block. The basic equation of leakage current is shown in Eq. (1) [17].

(1)$${\mathit{I}}_{\mathrm{leakage}}=I_{\mathrm{sub}}+I_{\mathrm{ox}},$$

where I_sub = sub-threshold leakage current, I_ox = gate-oxide leakage current.

(2)$$I_{\mathrm{sub}}=K_{\mathrm{1}}W{e}^{\frac{{\mathit{V}}_{\mathrm{TH}}}{\mathit{n}{\mathit{V}}_{\theta }}}\left(\mathrm{1}-e^{\frac{\mathit{V}}{{\mathit{V}}_{\theta }}}\right),$$

where K₁ = transconductance parameter (k= µC_ox), W = gate width, V_TH = threshold voltage, n = slope shape factor, V_θ = thermal voltage.

(3)$$I_{\mathrm{ox}}=K_{\mathrm{2}}W{\left({\displaystyle \frac{V}{T_{\mathrm{ox}}}}\right)}^{\mathrm{2}}{e}^{\frac{\alpha {\mathit{T}}_{\mathrm{ox}}}{\mathit{V}}},$$

where K₂ = transconductance parameter (k= µC_ox), α = experimentally derived factor, T_ox = oxide thickness.

Tab.4 Leakage current consumption (unit: nA)

	temperature
	27°C			110°C
voltage/V	0.7	0.9	1	0.7	0.9	1
conventional	4761	18250	27747	4284	14116	21475
Tri-mode	27.86	48.42	89.07	27.43	53.33	92.46
dual-switch	43.73	47.97	49.72	42.72	47.35	49.71
TTH	43.94	48.15	50.19	43.14	47.81	50.03
TTL	48.96	53.15	55.32	50.92	56.31	58.81

The noise aware MTCMOS techniques provided maximum reduction of leakage current in sleep mode, as shown in Fig. 13. Tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) circuit reduce the leakage current by 99.72%, 99.73%, 99.74% and 99.7% respectively, as compared to conventional circuit at 25°C. The dependence of sub-threshold leakage current on temperature is stronger than the gate leakage current [13]. At 110°C, the sub-threshold leakage current of a circuit is major power consumption in sleep mode. Tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) are reduced leakage current by 99.62%, 99.65%, 99.66% and 99.6% respectively, as compared to conventional circuit.

Fig.13 Percentage leakage current reduction provided by different MTCMOS circuit techniques as compared to conventional circuit (sleep mode)

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3.3 Active power

The active power of multiplier with tri-mode, dual–switch and tri–controlled–transistor (TTH and TTL) circuit techniques was evaluated in this section. The active power consumption of different circuits is shown in Table 5, at room temperature (27°C).

Tab.5 Active power consumption (unit: mW)

	transistor size
	2.67 nm	10 nm	15 nm
conventional	74.03
tri-mode	27.89	27.93	27.94
dual-switch	41.41	41.84	41.67
TTH	41.87	41.77	41.87
TTL	41.65	41.83	41.95

The dynamic switching power consumption of CMOS circuit is [18]

(4)$$P=C_L{V}_{\mathrm{DD}}^{\mathrm{2}}f,$$

where C_L is load capacitance, V_DD is supply voltage, and f is operating frequency.

Due to resistive voltage drop across the parker, dozer and dual-switch transistors, the effective supply voltage is lower in MTCMOS multiplier as compared to conventional multiplier. The active power consumed by the circuits is explained in Table 5. It is clear from table that, tri-mode, dual-switch and tri-transistor-controlled (TTH and TTL) technique reduced active power by 62.32%, 44.06%, 43.44% and 43.73% respectively, as compared to conventional circuit.

4 Conclusions

In this paper, ground bounce noise was investigated for standard MTCMOS circuit. Different MTCMOS techniques were used to reduce the ground bounce noise of the circuit. The ground bounce noise generation mechanisms during the sleep-to-active mode transition were identified. A two-step activation scheme with an intermediate mode was used in MTCMOS.

Tab.6 Performance comparison of different MTCMOS circuits

primary design metric	best technique	worst technique
ground bounce noise	voltage scaling	TTL	tri-mode
	transistor size	dual-switch	tri-mode
	temperature	TTL	tri-mode
leakage current	27°C, 0.7 V	tri-mode	TTL
27°C, 0.9 V or 1 V	dual-switch	tri-mode
active power consumption	tri-mode	TTL

Dependence of the size of additional controlled transistor, the lowest ground bounce noise was produced by TTL technique among the MTCMOS circuits. The TTL technique reduced the ground bounce noise by 78.82% compared to conventional circuit. Dual-switch technique reduced the leakage current by 99.73% compared to conventional circuit. Tri-mode technique reduced the active power by 62.32% compared to conventional circuit. Table 6, shows the different noise aware combinational MTCMOS circuits with different metric. It is clear from Table 6, that ground bounce noise is greatly reduced by TTL circuit in comparison to tri-mode circuit in voltage scaling and temperature variation. The dual-switch circuit is best to reduce the leakage current in comparison to other techniques. Tri-mode circuit is the best technique to reduce the active power of the circuit as comparison to other circuit techniques.

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Acknowledgements

The authors are very grateful to those who participated in this research work. There is no financial support for this research work.

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