The synthesis of two-dimensional materials for post-Moore integrated circuits

Abstract

With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore’s Law is approaching its physical limits. Two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigate short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature (< 450 °C) synthesis techniques. Additionally, this review summarizes innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, this review discusses strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, this review delineates the major technical challenges and potential optimization directions for 2D transistors. This review is confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology.

Graphical abstract

Keywords

synthesis / two-dimensional / semiconductor materials

1 Introduction

Centered on Complementary Metal−Oxide−Semiconductor (CMOS) technology, integrated circuits have become essential components in microprocessors, Static Random-Access Memory (SRAM), and various digital logic circuits [1, 2]. However, as channel lengths approach the 5-nm regime, traditional three-dimensional (3D) stacked chip architectures exhibit unit-area thermal densities that surpass silicon’s transient thermal capacitance limit, thereby destabilizing channel materials. Furthermore, with continued scaling of channel dimensions, short-channel effects and quantum tunneling phenomena become pronounced, leading to elevated leakage currents in semiconductor devices and a significant increase in power consumption [3−6]. As a result, Moore’s law faces imminent limitations, posing severe challenges to the future advancement of integrated circuits [7].

In recent years, two-dimensional (2D) materials have garnered significant attention from researchers due to their unique properties and ultrathin thickness [8−11]. 2D semiconductor materials, including transition metal sulfur compounds (TMDCs) and black phosphorus, have seen remarkable advancements in high-frequency electronic devices [12, 13], and optoelectronic integration [14−16], leveraging their atomic-scale thickness to exhibit quantum confinement effects, ultra-high carrier mobility, and in-surface anisotropy [17, 18]. In addition to TMDCs and black phosphorus, MXenes have recently emerged as an important family of 2D materials. While most MXenes are intrinsically metallic, surface termination engineering, elemental doping, and controlled oxidation have been shown — both theoretically and experimentally —to induce semiconducting phases with tunable bandgaps. Owing to their high carrier mobility, versatile chemistry, and compatibility with flexible substrates, semiconducting MXenes are attracting growing attention as promising candidates for post-Moore integrated circuits. Unlike conventional semiconductor devices, the naturally passivated surface of 2D semiconductors eliminates dangling bonds, thereby significantly reducing interfacial scattering and impurity trap scattering [19]. Moreover, 2D semiconductors possess sub-threshold swing (SS) values approaching the Boltzmann limit, offering a transformative technological pathway for achieving ultra-low power consumption and high integration density in the post-Moore era [20−22]. Additionally, their ultrathin nature effectively suppresses the short-channel effect, enhancing switching speed and minimizing power consumption [23, 24]. The compatibility of 2D materials with flexible substrates further promotes the development of flexible electronics and enables opportunities for 3D heterogeneous integration [25, 26]. Furthermore, the bandgap of certain 2D semiconductor materials is tunable, which is important for optimizing the performance of logic circuits and holds great potential for ultra-high-density 3D integration [27]. In this context, 2D materials emerge as promising candidates for overcoming the limitations of Moore’s law.

2D transistors continue to evolve, yet numerous challenges remain to be addressed. For the post-Moore-era transistor technology of 2D semiconductor materials, the growth of high-quality, large-area 2D semiconductor materials is a critical aspect [28, 29]. However, 2D materials exhibit randomly distributed nucleation points and equivalence between antiparallel islands during growth. Additionally, their growth modes are highly susceptible to perturbations from various factors, including temperature gradients and airflow, which significantly hinder the continuous growth of high-quality thin films [30−33]. Currently, integrated devices based on 2D semiconductors necessitate high dielectric constant and wide bandgap gate insulators to reduce the gate leakage and enhance the overall gate controllability, and provide high interface quality and dielectric reliability. Moreover, the integration of traditional 3D dielectric materials often results in a significant number of dangling bonds at the interface, which can degrade the carrier mobility of semiconductor material. Achieving optimal contact between 2D semiconductor materials and metal electrodes at the nanoscale remains a substantial challenge. Specifically, Fermi level pinning and pronounced Schottky barriers adversely impact the electrical properties and contact resistance of 2D semiconductor materials, thus hindering their industrial applications [34, 35]. In this review, we focus on 2D transistors, and presenting the latest advancements in the growth of 2D semiconductor materials and 2D dielectric materials. We then explore strategies for enhancing the contact between 2D semiconductors and metal electrodes. Subsequently, we highlight the progress of 2D transistors in large-scale integration and advanced applications. Finally, we offer conclusions and outlooks on 2D transistors.

2 Synthesis of channel materials

2.1 Unidirectional alignment epitaxial growth via substrate engineering

Based on the mechanistic analysis of the chemical vapor deposition (CVD) process, in which the thermodynamic driving force is regulated by the temperature field, the enhanced atomic diffusion capability can significantly improve the growth rate at higher growth temperatures. The kinetic limitation mainly originates from the substrate surface interface characteristics, which is manifested as the competitive relationship between the mean free range of adsorbed atoms (λ) and the substrate step spacing (L): when λ > L, most adsorbed atoms desorb before migrating to the step edge, resulting in a significant reduction of the growth rate; when λ < L, the adsorbed atoms can efficiently arrive at the edge of the nucleus and realize the growth rate close to the theoretical limit. It is worth noting that under fixed thermodynamic parameters, λ and L are completely determined by the substrate properties, and thus the interfacial interactions between the substrate and precursor atoms become a key parameter in regulating the nucleation kinetics. Based on this, substrate engineering has been shown to be an effective strategy to achieve controlled preparation of 2D materials at the wafer level, especially for single-crystal thin film growth by constructing seamless splicing structures. In this section, we take atomic surface smoothness, lattice matching, and space group symmetry as typical systems, and systematically review the research progress of substrate engineering in wafer-scale 2D materials preparation in recent years, and deeply analyze the design principles and implementation paths of different substrate engineering strategies, from the atomic-scale interface regulation mechanism to the macroscopic-scale experimental validation [36−38].

While CVD technology on transition metal-catalyzed substrates allows for the controlled preparation of wafer-scale single-crystal 2D materials, its industrial application requires the transfer of 2D materials to dielectric substrates for electrical functionalization. However, the mechanical transfer process inevitably introduces defects such as folds, cracks, and interfacial contamination, leading to significant degradation of electrical properties. Therefore, the development of direct epitaxy of 2D materials on insulating substrates has become a key path to break through the bottleneck of industrialization. The Fang team has successfully realized the highly oriented epitaxial growth of 2D semiconductor single crystals on C-surface sapphire substrates [Fig. 1(a)]. By rotating the crystal orientation by 30°, the compressive and tensile stresses are effectively regulated, and strain tolerance is realized, resulting in a controlled interfacial strain between the heterogeneous epitaxial single crystal with different lattice constants and the sapphire substrate. Photodetectors based on this heterogeneous epitaxial material show better photodetection performance than non-epitaxial devices [39]. A similar strategy has also been validated in the system of TMDCs: Loh’s group [40] utilized the ultra-low surface energy property of molten glass to successfully prepare 2.5 mm-scale single-crystal MoSe₂ triangular flakes [Fig. 1(b)], which showed a 40% enhancement of photoluminescence intensity compared with mechanically exfoliated samples [40]. Liu et al. [41] proposed a double-coupled synergistic tuning of the two-dimensional material with the intra-insulating substrate surface by van der Waals (vdW) coupling interaction and step interactions in a new mechanism of dual-coupling synergistic regulation, realizing the epitaxial preparation of 2-inch single-layer monocrystalline WS₂. Kong et al. [42] proposed a new strategy to realize the epitaxial growth of 2D semiconductor monocrystalline wafers, represented by molybdenum disulfide, on commercial insulator substrates, providing a solid material foundation for the large-scale industrial application of 2D semiconductors. These advances demonstrate that insulator substrate engineering offers innovative solutions for device-level integration of 2D materials with both interface quality and process compatibility.

The epitaxial growth mechanisms of 2D materials and 3D bulk thin films are fundamentally different, although both are based on heterogeneous nucleation on the substrate surface. In the 3D thin-film system, the material is strongly coupled to the substrate through oriented chemical bonding, and the epitaxy process has stringent requirements for lattice symmetry matching and lattice constant agreement (typically Δa/a < 5%). In contrast, the growth mechanism of 2D layered materials exhibits unique cross-dimensional properties: atoms within the layers build a stable 2D lattice through strong covalent/ionic bonds (binding energy ~2−8 eV/atom), while interlayer and layer-substrate interactions are dominated by weak vdW forces, with an energy scale 1–2 orders of magnitude lower than that of chemical bonds. This weak interfacial coupling property allows the epitaxial growth of 2D materials to break through the rigid constraints of conventional lattice matching and exhibit significant non-strict lattice matching dependence [43−45]. The Bi₂Te₃ can even form high-quality heterogeneous epitaxial structures on FeTe substrates with very different lattice structures [Fig. 1(c)] [46]. Controlling the thickness of two-dimensional materials is crucial for regulating the properties of two-dimensional materials, so the ability to grow large-area two-dimensional channel materials with different layers is of great significance for the development of two-dimensional semiconductors, and most of the current growth methods are unable to achieve stable growth of large-area, multilayer two-dimensional channel materials. Liu et al. [47] proposed an edge-aligned double-layer nucleation strategy based on an edge nucleation mechanism. By employing a CVD method, they achieved uniform nucleation and epitaxial growth of bilayer MoS₂ on a sapphire substrate with step height precisely controlled through high-temperature annealing. Furthermore, compared to traditional single-layer MoS₂ thin films, the bilayer MoS₂ devices synthesized by this method exhibited significantly enhanced mobility and improved short-channel current density, demonstrating superior performance characteristics [47]. It is worth noting that although the energy scale of the vdW interaction is low, its spatial distribution characteristics are decisive for the growth morphology of the 2D material: by tuning the lattice symmetry, step density, and other parameters on the substrate surface, the crystal orientation, domain size, and layer distribution of the 2D epitaxial layer can be precisely manipulated. This weak-coupling-strong regulation dialectic provides a unique physical basis for heterogeneous integration of 2D materials.

Although the heterogeneous epitaxial growth of 2D materials can be realized in a variety of substrate systems, the evolution of its crystallographic orientation is strictly limited by the symmetry matching principle at the substrate-film interface. Analyzed from the thermodynamic perspective of interfacial energy optimization, the 2D epitaxial process is essentially a dynamic selection mechanism of the coupling of adsorbed atoms with the potential field on the substrate surface, and the 2D crystal core edges tend to extend along the direction of low interfacial energies determined by the substrate lattice symmetry, resulting in the formation of a stable domain structure with a specific crystallographic orientation [48]. Based on the principle of lattice symmetry subgroup matching, Ma et al. demonstrated a versatile method for the growth of dense, aligned arrays of MoS₂ nanoribbons by CVD on anisotropic sapphire substrates without the need for customized surface steps. This method is capable of synthesizing nanoribbons with widths below 10 nm and longitudinal axes parallel to the sawtooth direction, and can be extended to the growth of WS₂ nanoribbons and MoS₂−WS₂ heterogeneous nanoribbons, as shown in Fig. 2(a) [49]. The mechanism is also validated in the tetragonal symmetric system, where the lattice orientation of the quadruple-symmetric Bi₂O₂Se film is confined to be aligned along the [100]/[010] direction of the substrate when the film is grown on a cubic-symmetric SrTiO₃(001) substrate, as shown in Fig. 2(b). This stems from the uniaxial orientation-locking effect due to the interfacial energy anisotropy of tetragonal-phase films with cubic substrates [50]. It is worth noting that although the symmetry matching strategy exhibits universality in centrosymmetric material systems, the epitaxial orientation regulation mechanism for complex interfacial systems with asymmetric surface reconstruction or mirror-symmetry breaking requires further decoupling of the nonlinear correlation between the interfacial potential field distribution and the dynamic growth process.

Preparation of TMDCs with non-centrosymmetric lattice structures faces the key challenge of compatibility between symmetric substrates and catalytic substrates, which has prompted researchers to explore novel substrate design strategies from an energy-modulation perspective. Crystal nucleation tends to occur at step edges rather than flat surfaces, which stems from the fact that step sites have the lowest interface formation energy. By designing and processing substrates with controllable step structures, the unidirectional orientation of two-dimensional crystal domains can be effectively guided. Kim et al. [51] obtained Au (111), (110), and (100) crystal faces, providing a universal platform for the growth of materials with different symmetries. Liu et al. [41] grew wafer-scale single-crystal monolayers of WS₂ with dual symmetry as shown in Fig. 2(c). Wang et al. [52] optimized the direction of miscutting of c-face sapphire to the a-axis, and successfully grew 2-inch single-crystalline MoS₂ thin films, whose crystalline quality and electrical properties meet the standards for industrial applications, as shown in Fig. 2(d). Together, these results show that the step-edge-induced nucleation control and symmetry-breaking design based on step edges can break through the limitations of traditional centrosymmetric substrates on the intrinsic physical properties of materials.

This paper systematically describes the key role of substrate-assisted growth in CVD technology for the controlled preparation of 2D materials at the wafer level. These advances not only reveal the mechanisms of substrate-material interface interactions on the regulation of nucleation kinetics at the atomic scale, but also promote the device-level integration of 2D semiconductors with topological insulators and other materials at the macroscopic scale. Through the synergistic thermodynamic optimal orientation and kinetic path design, substrate engineering provides innovative solutions for breaking through the mechanical transfer defects and realizing the large-scale preparation of high-performance 2D materials, which lays the foundation for its application in the future electronics and optoelectronics fields.

2.2 Seed-induced epitaxy growth

Although step-guided epitaxy growth provides a promising approach for the synthesis of wafer-scale single-crystalline 2D materials with a single orientation, the need for meticulous substrate and inevitable transfer process pose challenges for commercial integrated circuits. To overcome these problems, a seed-assisted technique was used for homogeneous epitaxial growth of large-area 2D materials [54]. Xu et al. [55] successfully prepared 1-inch single crystal 2H-MoTe₂ films by pre-implanting small area single crystal 2H-MoTe₂ seeds on the surface of polycrystalline 1T'-MoTe₂. Figure 3(a) shows the schematic diagram of in-plane seed-induced epitaxy growth of wafer-scale single-crystalline 2H MoTe₂. Due to the abundance of Te vacancies in 1T′-MoTe₂, the continuous introduction of external Te atoms induces the phase transition and recrystallization of MoTe₂ from 1T′ to 2H. Meanwhile, a dense Al₂O₃ film covers the wafer surface, with a small hole created in the seed area as the sole channel for Te atoms, thereby preventing the spontaneous, disorderly nucleation of 2H-MoTe₂ [Fig. 3(b)]. As the epitaxial growth of 2H-MoTe₂ is triggered by a pre-implanted single-crystal seed as the template and the growth process does not rely on the substrate structure, large-scale device arrays can be directly fabricated on the target substrate without an additional transfer process, thereby ensuring the integrity and electrical performance of the channel material. In addition, scalable single-crystalline 2D p-type 2H-MoTe₂ transistor arrays were fabricated using a similar epitaxial strategy, achieving high on-state currents (~ 7.8 μA/μm) and an on/off ratio (~ 10⁵), thereby promoting the development of next-generation 2D electronics for both front and back-end applications [56]. The traditional CVD preparation of large-area MoS₂ typically requires prolonged processing times, posing significant barriers for industrial applications. Liu et al. [57] developed a novel two-dimensional Czochralski (2DCZ) growth method, enabling seamless growth of centimeter-scale single-crystal MoS₂ domains by constructing a 2D liquid precursor film on a molten glass substrate and combining it with a rapid sulfidation process. This approach exploits the molten glass’s low nucleation barrier and surface tension to inhibit polycrystalline nucleation while promoting lateral crystallization, thereby achieving a grain-boundary-free single-crystal structure. Notably, the method achieves an ultrafast growth rate of up to 75 μm/s through rapid diffusion of the liquid-phase precursor, overcoming the critical limitation of conventional techniques in terms of processing efficiency [Fig. 3(c, d)] [57]. Han et al. [58] fabricated centimeter-scale 2D β′-In₂Se₃ films by introducing InSe seed crystals. Density functional theory (DFT) calculations reveal that when atoms are fully relaxed, the energy difference between β-phase and β'-phase monolayer In₂Se₃ monotonically increases with the rise in selenium vacancy concentration [Fig. 3(e)]. This indicates the β'-phase is more stable under selenium-deficient conditions. Consequently, at elevated temperatures, β-InSe acts as a seed crystal, facilitating the nucleation of β'-In₂Se₃. Benefited from controllable seed-induced epitaxy growth and phase-transition transfer methods, large-area synthesis of three phases of In₂Se₃ was achieved [Fig. 3(f)], rendering 2D In₂Se₃ a promising candidate for memory transistors and heterophase junctions. Due to independence from highly modulated substrates, seed-induced epitaxy growth provides a promising way for integration of 2D materials with other functional materials or architectures for the fabrication of integrated devices. In 2022, Pan et al. [59] achieved a direct synthesis of heteroepitaxy of single-crystal 2D MoTe₂ on highly lattice-mismatched substrates and 3D architectures [Fig. 3(g)]. As shown in Fig. 1(h), 2H-MoTe₂ single-crystal domains nucleated in the continuous polycrystalline 1T′ background and grew through an in-plane seed-induced epitaxy process and across the 3D fin structures. Meanwhile, a wafer-scale p−n heterojunction array was fabricated on an n-type silicon substrate [Fig. 3(i)], showing spatial uniformity of the electrical performance of the devices on a large scale.

Seed-induced epitaxy growth brings a platform to synthesis large-scale 2D single crystals on arbitrary substrates for CMOS integration. However, the growth dynamics are still unclear, and the types of 2D materials that can be grown by this method are still few.

2.3 Confined growth

To meet the demands of modern industry, it is imperative to achieve large-scale integration of 2D channel materials and their device manufacturing [8, 25, 60−62]. Among the various methods for growing two-dimensional channel materials over large areas, it is difficult to precisely control the growth of materials in a specified area. While confined growth fulfills this requirement [63−65]. By confined growth, this method effectively addresses challenges in conventional large-area growth, such as grain boundaries [14, 66], amorphization [67, 68], and mismatches between in-plane and out-of-plane growth rates [69], enabling the fabrication of large-area single-crystal 2D material arrays. In 2015, Zheng et al. [70] employed a NaCl solution stamping method to synthesize Bi₂Se₃ and In₂Se₃ arrays. As shown in Fig. 4(a), similarly, In 2015, our group [71] used standard mechanical exfoliation to transfer graphite onto SiO₂/Si substrates, followed by gravure printing of mica in NaCl solution using a polydimethylsiloxane (PDMS) stamp, and subsequent CVD growth of PbS on the NaCl-masked mica substrate yielded ordered PbS arrays [Fig. 4(e)]. In 2024, Zhang et al. [72] developed hydrophilic square prism arrays via glass-etching observed in Fig. 4(b), with hydrophobic modification of surrounding regions, and by exposing the droplet array to anti-solvent vapor in a sealed chamber, perovskite crystals nucleated and grew owing to reduced solubility, ultimately forming precisely aligned perovskite arrays (PACAs) after solvent evaporation. Figure 4(c) shows that Kim et al. [73] fabricated micron-scale trench arrays in a-SiO₂-coated c-Al₂O₃ or a-HfO₂/Si wafers, where selective growth of WSe₂ within the trenches allowed single-domain nucleation followed by lateral expansion, forming aligned WSe₂ arrays in 2023 [Fig. 4(f)]. In 2022, Zhang et al. [74] introduced laser patterning and anisotropic thermal etching to create periodic triangular hole arrays in 2D crystals presented in Fig. 4(d), enabling inside-out epitaxial growth of another 2D material and producing monolayer mosaic heterostructures (MHHs) with atomically sharp interfaces [Fig. 4(g)]. This process involved synthesizing large-area monolayer WS₂ single crystals via CVD, generating periodic point defect arrays using focused laser irradiation, thermally etching defects into triangular pores under controlled conditions, and growing WSe₂ laterally within the patterned WS₂ template to form MHHs. Compared to traditional lithography and plasma etching, this approach offers advantages such as atomic-precision etching with high selectivity while avoiding lithography-induced contamination, which can propagate through process steps, cause uncontrolled nucleation, and lead to heterogeneous multilayers.

As discussed above, confined growth is crucial for the fabrication of large-area 2D channel materials. Various methods, including NaCl solution stamping, substrate patterning and etching, and heterostructure TMD-layer etching, have been developed to achieve this goal. However, the size of individual regions within confined-growth arrays is often limited by factors such as material properties and substrate characteristics. To obtain arrays with larger individual areas and thinner thicknesses, further development of simple and effective strategies based on spatially confined methods is essential.

2.4 Low-temperature growth

2.4.1 Low-temperature synthesis of 2D channel materials by metal-organic chemical vapor deposition (MOCVD)

With the advent of sub-5 nm semiconductor device technology, the thermal budget constraints of conventional high-temperature epitaxial processes have led to increasingly prominent issues such as interfacial misalignment, lattice distortion, and doping diffusion, which have emerged as critical bottlenecks restricting the further advancement of CMOS device performance. Notably, the integration of 2D semiconductor materials with existing CMOS back-end processes (BEOL) processes mandates temperatures below 450 °C to ensure compatibility [75, 76]. In this context, low-temperature growth technologies represent a fundamental breakthrough to circumvent the physical and engineering limitations inherent in traditional high-temperature methodologies [77, 78].

In the growth methods of 2D channel materials, MOCVD is a particularly promising approach and has become one of the mainstream techniques for low-temperature [79], large-area synthesis of 2D semiconductor materials [80−82]. MOCVD operates by decomposing metal-organic precursors to release metal atoms or nanoparticles, which then react on the surface of the target substrate to form semiconductor thin films. Compared to conventional CVD technologies, MOCVD exhibits higher precision control, superior uniformity, and enhanced low-temperature compatibility [83, 84].

In 2015, Kang et al. [76] successfully achieved wafer-scale growth of 2D MoS₂ and WS₂ films on SiO₂ substrates using MOCVD, demonstrating exceptional electrical performance. The study employed molybdenum hexacarbonyl [Mo(CO)₆] and tungsten hexacarbonyl [W(CO) ₆] as metal precursors, which thermally decompose to release metal atoms. Diethyl sulfide [(C₂H₅)₂S] was used as the sulfur source, releasing sulfur atoms via a hydrogen-assisted reduction reaction. All reactant gases were mixed in a hydrogen (H₂) environment and transported to a high-temperature reaction chamber. Notably, the growth temperature for single-layer MoS₂ and WS₂ was reduced to as low as 550°C, significantly lower than the ~800 °C required by traditional CVD methods. The resulting MoS₂ films exhibited room-temperature carrier mobilities of ~30 cm²·V⁻¹·s⁻¹ (increasing to ~114 cm²·V⁻¹·s⁻¹ at 90 K) with on/off current ratios approaching 10⁶, while WS₂ devices achieved mobilities up to 18 cm²·V⁻¹·s⁻¹ with similar on/off ratios of ~10⁶, and the lateral growth rate of MoS₂ domains reached ~2–3 μm/min. Mun et al. [85] proposed a kinetics-controlled MOCVD method to directly grow high-quality monolayer MoS₂ films on polyimide (PI) substrates at a low temperature of 250 °C. By precisely controlling the feeding rate and dosage of NaCl, this work introduced alkali-metal catalysts to suppress nucleation density and enhance surface atomic diffusion capability, achieving wafer-scale uniform growth. Additionally, the integration of silanized SiO₂ buffer layers and glass-supported flexible PI substrates addressed issues of thermal deformation and surface contamination in polymers. Electrical characterization showed that MoS₂ films on SiO₂/Si exhibited mobilities of ~10 cm²·V⁻¹·s⁻¹ with on/off ratios up to 10⁷, while devices on PI substrates maintained ~1 cm²·V⁻¹·s⁻¹ and ~10³, respectively. Even at the reduced growth temperature, the devices operated at microwatt-level power and displayed low defect densities comparable to high-temperature CVD films. The films expanded laterally at ~1–2 μm/min.

Song et al. [86] developed a pulsed-flow MOCVD method to achieve wafer-scale growth of 2D InSe films on c-plane sapphire substrates at temperatures as low as 350–500 °C. By modulating the Se precursor flux through pulsed delivery, they dynamically controlled the Se/In ratio to suppress the formation of the In₂Se₃ phase and promote layer-by-layer growth of InSe. The pulsed-flow technique also prevented the formation of In-rich droplets, enabling lateral coalescence of InSe domains into continuous thin films with thickness controllability (from monolayer to few layers). The InSe films exhibited room-temperature carrier mobilities of 20–25 cm²·V⁻¹·s⁻¹ with on/off ratios of 10⁵–10⁶, demonstrated μs–ms switching speeds, and stable operation at microwatt-level power consumption. Moreover, their defect density was low — comparable to that of high-quality epitaxial InSe single crystals — and the process achieved a lateral growth rate of ~3–4 μm/min. A recent breakthrough by Zhu et al. [87] has demonstrated a revolutionary low-temperature growth process that enables efficient, uniform wafer-scale monolayer MoS₂ growth directly on silicon wafers in less than one hour, with temperatures below those required by current CMOS BEOL processes [Fig. 5(a, b)]. The researchers have developed a novel tubular furnace system custom-engineered for MOCVD, featuring two vertically separated chambers, a low-temperature (250 °C) front chamber for silicon wafer placement and Mo(CO)₆ precursor, and a high-temperature (550 °C) rear chamber for pyrolyzing the sulfur precursor (C₂H₅)₂S to generate reactive sulfur radicals. The silicon wafers are vertically positioned to avoid thermal damage from the high-temperature region, and ensuring uniform precursor delivery across the entire 200 mm wafer scale. In the high-temperature chamber, the sulfur precursor (C₂H₅)₂S is thermally decomposed to generate reactive sulfur species, while the low-temperature chamber receives these sulfur species via heat conduction, this can preventing excessive decomposition of the Mo(CO)₆ precursor. This dual-zone design allows directional MoS₂ growth at low temperatures. By dynamically adjusting the pulse frequency and duty cycle of Mo(CO)₆, the team precisely controls the instantaneous Mo flux to balance nucleation density and grain growth rates, ultimately achieving wafer-scale uniform monolayer films. This method not only enables a short growth time but also operates at significantly lower temperatures, making it highly compatible with existing CMOS manufacturing processes and an ideal solution for large-scale integration of 2D materials into semiconductor devices [Fig. 5(c)]. Furthermore, using this method, MoS₂ transistors were successfully integrated directly onto silicon CMOS circuits at a growth temperature of 250 °C. The devices exhibited room-temperature mobilities of 28–35 cm²·V⁻¹·s⁻¹ with on/off ratios up to 10⁷, demonstrated μs-level switching speeds, operated at microwatt power, and showed low defect densities comparable to high-temperature CVD films, underscoring the promise of this approach for CMOS-compatible 2D integration [Figs. 5(d, e)], with a lateral growth rate of ~5 μm/min. Hoang et al. [88] successfully synthesized high-quality, highly crystalline monolayer MoS₂ on PI and glass substrates using a similar method [Figs. 5(f)−(i)]. Notably, their work employed dimethyl sulfide (DMS, (CH₃)₂S) as the sulfur source and positioned the high-temperature zone upstream while the low-temperature zone was downstream. The researchers developed a low-temperature (150 °C) MOCVD process. First, a mixed precursor solution of Mo(CO)₆ and DMS was prepared. Subsequently, deposition occurred in a thermally wall asymmetric three-zone MOCVD system with two-stage flow rate control — initial low flow for nucleation and subsequent high flow for film expansion. The system’s extended high-temperature zone ensured stable growth at 150 °C, while slow cooling in an H₂S environment suppressed sulfur vacancies. This method eliminated substrate transfer steps, directly achieving wafer-scale uniform MoS₂ films (grain size up to 800 nm) on flexible and glass substrates. The resulting films exhibited the transistors delivering electron mobilities of 9.1 cm²·V⁻¹·s⁻¹, on/off ratios of 10⁵–10⁶, and microwatt-level power consumption. Structural analyses confirmed low defect densities with effectively suppressed sulfur vacancies, highlighting the robustness of this ultra-low-temperature MOCVD strategy [Fig. 5(j, k)], and the lateral growth rate reached ~2 μm/min at 150 °C.

2.4.2 Low-temperature synthesis of 2D channel materials by other methods

In addition to MOCVD methods for low-temperature growth of 2D channel materials, researchers are now exploring alternative approaches such as low-melting-point precursors [89−91], plasma enhanced chemical vapor deposition (PECVD) [92−94], vdW epitaxial substrates [95, 96], tellurium-assisted growth [97], and salt-assisted growth [98−100]. Recently, Moon et al. [101] proposed a novel hypotaxy growth method that enables direct wafer-scale synthesis of 2D channel materials on various substrates at 400°C, making it compatible with CMOS BEOL [Figs. 6(a)−(f)]. This graphene-assisted sulfidization/selenization technique realizes low-temperature epitaxial growth of single-crystal TMDs through metal film (e.g., Mo) sulfuration on non-crystalline or lattice-mismatched substrates. Initially, MoS₂/MoSe₂ nuclei aligned with graphene are formed at 1000°C via sulfurization, followed by vertical-oriented crystal growth as graphene is etched and sulfurizing gas penetrates. By oxygen plasma pretreatment of graphene to introduce nanopores, the growth temperature can be reduced to 400 °C, overcoming traditional epitaxial limitations requiring high temperatures and specific substrates. This method demonstrates precise thickness control from monolayer to multilayer (up to 100 layers), producing MoS₂ films with exceptional properties including 120 W·m⁻¹·K⁻¹ thermal conductivity and 87 cm²·V⁻¹·s⁻¹ electron mobility. It has been successfully extended to other TMD systems (MoSe₂, WS₂) and holds great promise for 3D monolithic integration. This method achieved lateral growth rates of ~3–5 μm/min, producing MoS₂ with an electron mobility of 87 cm²·V⁻¹·s⁻¹, μs–ms switching speeds, microwatt-level power consumption, and low defect densities approaching epitaxial single-crystal quality.

Kim et al. [102] developed a low-temperature single-crystal 2D semiconductor growth technique based on geometrically constrained selective epitaxy by designing an array of silica mask microgrooves at specific edge angles on an amorphous hafnium oxide (a-HfO₂) substrate, exploiting the chemical bonding enhancement effect and nucleation principle of the edge sites and combining with a dual-temperature CVD system to realize a single-crystal at 380−385 °C MoS₂/WSe₂ epitaxy [Figs. 6(g)−(k)]. By regulating the microgroove dimensions to confine the lateral growth range, ensuring single-nucleus nucleation and lateral monolayer growth, high-quality single-crystal thin 2D semiconductor channel materials films with a mobility of >50 cm²·V⁻¹·s⁻¹ is obtained. The films exhibited a lateral growth rate of ~3–4 μm/min, electron mobilities exceeding 50 cm²·V⁻¹·s⁻¹, μs-level switching speeds, and microwatt-level power operation, with extremely low defect densities comparable to high-temperature epitaxial single crystals. Huang et al. [103] recently developed a pressure-assisted liquid-metal printing technique to achieve controlled growth of β-Ga₂O₃ thin films at 150°C under solvent-free, ambient air conditions without vacuum [Figs. 6(i, m)]. By leveraging the oxide skin formed during liquid gallium oxidation as a precursor and tuning external pressures between 29–129 kPa, they successfully fabricated polycrystalline β-Ga₂O₃ nanosheets with a thickness of ~3 nm. The resulting n-type thin-film transistors (TFTs) exhibited exceptional performance: a saturation mobility of 11.7 cm²·V⁻¹·s⁻¹, on/off-current ratio of 10⁸, and subthreshold swing of 163 mV·dec⁻¹. Low-temperature growth is crucial for the development of 2D semiconductors, as traditional CVD techniques are severely limited by their high-temperature requirements. With continuous advancements in low-temperature growth technologies, industrial applications of 2D semiconductors are expected to be further propelled. Moreover, the pressure-assisted liquid-metal printing route is inherently compatible with flexible polymeric or ultrathin glass substrates due to its low-temperature and solvent-free nature. Such direct integration greatly facilitates the development of flexible and wearable electronics, where β-Ga₂O₃ dielectrics can serve as robust gate insulators while maintaining mechanical compliance. These attributes underscore the potential of liquid-metal–printed dielectrics not only for rigid wafer-scale integration but also for emerging applications in bendable displays, conformal sensors, and foldable circuits [103, 104].

3 Synthesis of dielectric layers

2D materials have great potential in device applications due to their unique properties. However, the conventional dielectrics used in current silicon-based processes are not compatible with 2D channel materials [47], as the vdW surface and ultra-thin thickness of 2D materials lead to severe performance degradation by the various dangling bonds on the conventional dielectrics, and it is also very difficult for the conventional processes to deposit high-quality dielectrics on the surface of 2D materials due to the inert surface of 2D materials. It is also very difficult to deposit high quality dielectrics on the surface of 2D materials by conventional processes due to the inert surface of 2D materials, so it is crucial to synthesis dielectric layers that is more compatible with 2D channel materials.

3.1 Synthesis of two-dimensional dielectric layers by CVD method

CVD is a widely utilized technique for synthesizing various high-quality dielectric materials as gate dielectrics in 2D electronic devices. Hexagonal boron nitride (hBN), as a 2D layered dielectric, has potential for scalable integration into the semiconductor industry [105, 106]. In 2024, Li et al. [107] successfully grew high-quality singlecrystal monolayer hBN films on Cu(111) foils by merging the wellaligned, unconventional hexagonal-shaped hBN islands via CVD. The schematic process for preparing hBN is showed in Fig. 7(a). Trace oxygen during CVD growth modulates the energies of B-/N-terminated edge, steering hBN island morphology toward hexagonal over triangular shape. Besides, layered 2D dielectrics with higher-κ values above hBN (κ = 2−4) have made great progress in recent years. In 2024, Xu et al. [108] reported the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride- hydrate-assisted CVD method with high dielectric constant of 15.3. Meanwhile, Shi et al. [109] recently demonstrated synthesis of wafer-scale (2-inch) single-crystalline LaOCl/SmOCl monolayers on c-Al₂O₃ by flux-assisted CVD strategy. In 2023, Chen et al. [110] demonstrated CVD-grown Bi₂SiO₅ (κ > 30), while Tan et al. [111] reported a FinFETs array based on Bi₂O₂Se/Bi₂SeO₅ epitaxial heterostructures exhibiting an electron mobility of 270 cm²·V⁻¹·s⁻¹.

Nonlayered oxides (Al₂O₃, HfO₂) are still an indispensable family in CMOS dielectric layer [112], while CVD growth of ultrathin high-κ dielectric that can provide high interface quality and reduce electrically active traps is a significant direction. Very recently, our group demonstrated 2D monocrystalline gadolinium pentoxide (Gd₂O₅) synthesized by vdW epitaxy on the mica, exhibiting high-κ and wide-bandgap [113]. Schematic of vdW epitaxial growth and OM image of Gd₂O₅ nanosheets as shown in Fig. 7(b). Frequency-dependent capacitance–voltage (C–V) measurements reveal high effective dielectric constant (ε_eff ~25.5 at 50 kHz) for 32 nm Gd₂O₅ and gradually decreases with the applied frequency until 0.5 MHz as shown in Fig. 7(c). The leakage current and breakdown field strength (EBD) in vertical graphite/7.2-nm Gd₂O₅/metal device devices as shown in Fig. 7(d). In 2024, Zhu and colleagues [114] realized ultrathin MgNb₂O₆ single crystals via buffer-controlled strategy in the nanoscopic space confined by vertically stacked mica nanosheets as shown in Fig. 7(e). They fabricated a top-gated monolayer MoS₂ FET array consisting of 20 individual devices [Fig. 7(f)] and exhibit both the average on/off ratio exceeding 10⁷ and the field-effect mobility with values of 21.5 cm²·V⁻¹·s⁻¹ as shown in Fig. 7(g). In 2024, Li et al. [115] developed a novel elements slow-supply CVD method, wherein the substrate was sandwiched between precursors to grow ultrathin α-CaCr₂O₄ crystals (~1.2 nm). Manganese oxide (Mn₃O₄) single crystal nanosheets with dielectric constant of 135 was successfully fabricated by Yuan et al. [116].

Sb-based oxides exhibit molecular crystal structure. In 2020, Yang et al. [117] synthesized high-quality SbO_1.93 single crystals on re-solidified Ag substrates fabricated by annealing Ag wire-deposited Co foil, achieving uniform Ag diffusion across the surface as shown in Fig. 7(h). In contrast to conventional oxides, SbO_1.93 exhibits superior electrical insulation performance, demonstrating both an enhanced dielectric constant (~100) and an exceptional breakdown electric field (57 MV·cm⁻¹) as shown in Fig. 7(i). In 2024, Wang et al. [118] synthesized α-Sb₂O₃ nanosheets (κ = 11.8, E_g = 3.78 eV) via a one-step CVD method, which enabled dual-gated MoS₂ FETs to achieve >10⁸ on/off ratios.

3.2 Synthesis of two-dimensional dielectric layers by physical vapor deposition (PVD)

Parallel to CVD, several advanced dielectrics synthesized via PVD have also emerged as promising gate dielectric candidates in 2D electronics. The conventional perovskite oxide SrTiO₃ stands out as a dielectric due to its ultrahigh static permittivity exceeding 300. However, its requirement for high-temperature growth and an epitaxial base poses a challenge for direct integration on 2D material surfaces. Recent advances in combining etching of water-soluble sacrificial layers with mechanical transfer enable the integration of high-κ single-crystalline SrTiO₃ onto 2D semiconductors [119, 120]. SrTiO₃ films can be epitaxially grown on a Sr₃Al₂O₆-buffered SrTiO₃ substrate using Pulsed Laser Deposition (PLD). After dissolving the Sr₃Al₂O₆ water-soluble sacrificial layer, the released SrTiO₃ films can be transferred onto target substrates with the assistance of the polymer support [Fig. 8(a)]. A back-gated field-effect transistor (FET) constructed with an SrTiO₃ gate dielectric and a MoS₂ channel exhibits high on/off ratio of ≈ 10⁶ and sub-threshold SS as low as 71.5 mV·dec⁻¹ [Fig. 8(b)]. The SrTiO₃ used as gate dielectrics exhibits superior performance in both equivalent oxide thickness (EOT) and SS compared to conventional dielectrics such as CaF₂ and HfO₂ [Fig. 8(c)].

Similarly, Sr₃Al₂O₆ is employed to fabricate large-area, crack-free (Ba,Sr)TiO₃ films, exhibiting large dielectric permittivity exceeding 3000 [121, 122]. However, these perovskite materials face issues of reduced dielectric property and lower breakdown field as the film-thickness decreases.

The channel material Bi₂O₂Se can be epitaxially grown on the SrTiO₃ surface using Molecular Beam Epitaxy (MBE), facilitating the integration of the 2D Bi₂O₂Se/SrTiO₃ heterojunction onto various substrates [Fig. 8(d)]. [123] The Bi₂O₂Se/SrTiO₃ heterostructure is strain-free, ensuring the high quality of the epitaxial films and device integration. Optical images show a back-gated transistor constructed using the transferred Bi₂O₂Se/SrTiO₃ heterostructure on silicon, and the FET exhibits an on/off ratio exceeding 10⁴, a minimum SS of 90 mV·dec⁻¹, and a leakage current density below 10⁻³ A·cm⁻² [Fig. 8(e)].

Simply through Thermal Evaporation (TE), inorganic molecular crystal Sb₂O₃ can work as a buffer layer on 2D semiconductors, forming a high-quality oxide-to-semiconductor interface, which offers a hydrophilic surface solving the difficulty of integration high-κ dielectric via Atomic Layer Deposition [Fig. 8(f)] [124]. The Sb₂O₃/HfO₂ heterostructure as a gate dielectric layer shows low EOT of 0.67 nm. Combining with MoS₂ as the channel material, it achieves an on/off ratio exceeding 10⁶ and an ultra-low SS of 60 mV·dec⁻¹ while operating at an ultra-low gate voltage of 0.4 V [Fig. 8(g)].

Similarly, through thermal evaporation, rare-earth metal fluorides achieve a high dielectric constant of ~30 and an ultra-low EOT thickness of ~0.15 nm. Based on this, the MoS₂ transistor demonstrates an on/off ratio exceeding 10⁸, a low SS of 65 mV·dec⁻¹, and a leakage current density of ~10⁻⁶ A·cm⁻² [125].

3.3 Synthesis of two-dimensional dielectric layers by new fabrication strategies

Unlike conventional fabrication methods, recent advancements in fabrication strategies offer state-of-the-art dielectric properties and industrial scalability for wafer-scale integration with 2D semiconductors, paving the way for practical applications in 2D semiconductor chips.

Metal thermal evaporation technology combined with the intercalation oxidation is employed to stably form an atomically thin, single-crystalline Al₂O₃ layer on the surface of epitaxial metal alumina films [126]. An epitaxial aluminum metal film is prepared onto a 4-inch graphite/Ge substrate, followed by peeling-off and intercalative oxidation. Through adjusting the oxidation time, the thickness of the Al₂O₃ layer can be precisely controlled [Fig. 9(a)]. During the oxidation process, the oxidation rate decreases from 2 nm·h⁻¹ to 0.8 nm·h⁻¹ as the oxidation time increased from 1 hour to 12 hours. The Al₂O₃ layer exhibited an ultra-high breakdown field of 17.4 MV·cm⁻¹ at a thickness of 2 nm, demonstrating significantly superior properties compared to other dielectrics [Fig. 9(b)]. In additionally, when integrated onto a top-gate transistor with MoS₂ as the channel material, it exhibited a SS of ≈ 76 mV·dec⁻¹, an on/off ratio of 10⁹, and an interface state density of 8.4 × 10⁹ cm⁻²·eV⁻¹. In addition, this method enables the intact transfer of a 4-inch patterned single-crystalline Al₂O₃ dielectric layer, along with the drain, source, and gate electrode array, onto a MoS₂ film on an Al₂O₃ substrate, allowing for the direct integration of a wafer-scale device array [Fig. 9(c)].

Utilizing squeeze-printing and surface-tension-driven techniques, an ultrathin oxide layer can naturally form on the surface of liquid Ga metal in an ambient environment, which allows the direct fabrication of an ultrathin and uniform native Ga₂O₃ layer on the surface of MoS₂ [Fig. 9(d)] [104, 127]. The native Ga₂O₃ layer exhibits a high dielectric constant of ~30 and an EOT of ~0.4 nm [Fig. 9(e)]. Owing to its exceptional dielectric properties and vdW integration, Ga₂O₃ top-gated MoS₂ transistors achieve an SS of 60 mV·dec⁻¹, an on/off ratio of up to 10⁸, a break-down field 11 MV·cm⁻¹ and a low gate leakage current of ~4 × 10⁻⁷ A·cm⁻². This strategy enables the fabrication of a large-area native Ga₂O₃ dielectric layer on the surface of MoS₂ films, dramatically simplifying wafer-scale device array integration [Fig. 9(f)].

Another interesting method for dielectric layers is synchronizing the thermal decomposition of metal salts and water-assisted forming, which allows for the mechanical exfoliation of 2D metal oxide flakes, enabling the fabrication of a wide variety of metal oxides, as well as ferroelectric materials [128].

2D perovskite oxide Sr₂Nb₃O₁₀ nanosheets were synthesized via calcination and liquid-phase exfoliation, exhibiting a high dielectric constant (24.6) and a moderate bandgap, making them suitable as photoactive high-κ dielectrics for integration into 2D optoelectronic devices [129].

An amorphous, transferable high-κ (42.9) copper calcium titanate films are synthesized via a wet chemistry-based method [130]. Their transferable nature enables harmless integration into 2D semiconductors, and visible light active properties enables an electrically controlled, optically activated nonvolatile floating gate.

Although 2D materials exhibit considerable potential for electronic device applications, their stability in real-world operational environments remains a critical challenge. High-temperature [131, 132] and mechanical stress [133, 134] conditions can lead to significant performance degradation. During thermal cycling, for instance, the weak interlayer bonding in 2D materials can result in thermal expansion mismatch, leading to the formation of cracks. Additionally, mechanical stress can propagate these cracks, particularly in large-area materials, exacerbating the problem. Beyond mechanical and thermal stability, environmental degradation is another major factor affecting the long-term performance of 2D materials [135]. Materials like black phosphorus, which are particularly prone to oxidation, may degrade when exposed to air, reacting with moisture and oxygen, which compromises their device performance. Recent studies have suggested several strategies, such as encapsulation, defect engineering, and surface modification, to mitigate these issues [136, 137]. These approaches are anticipated to play a key role in enhancing the long-term reliability and durability of 2D materials in industrial applications, enabling their more widespread use.

However, despite progress in small-scale experiments, large-scale production of 2D materials still faces significant obstacles. Uniform growth over large areas and consistent material properties remain unresolved, and existing synthesis methods such as CVD are limited by production rates and material uniformity. Moreover, the high cost of production, driven by expensive precursors, equipment, and energy consumption, presents another barrier. To achieve commercial viability, future research must focus on developing more cost-effective synthesis techniques and optimizing existing production processes to enable large-scale, low-cost production of 2D materials.

4 Synthesis of MXene

In addition to TMDCs and oxide semiconductors discussed in the previous sections, another rapidly emerging class of 2D materials is the family of MXenes (M_n+1XnT_x, where M is a transition metal, X = C/N, and T_x represents surface terminations such as −O, −OH, and −F). Discovered in 2011 [138], MXenes differ fundamentally from most other 2D materials in that they are produced via top-down selective etching of layered MAX phases rather than bottom-up growth. MXenes combine metallic conductivity with tunable surface chemistry and hydrophilicity, making them attractive for applications ranging from field-effect transistors and memristors to optoelectronic and energy devices. Importantly, recent studies indicate that the electronic properties of MXenes can be modulated by synthesis conditions, intercalation, and termination engineering, opening pathways toward semiconducting behavior.

Zhang et al. [139] recently reported a fluoride-free molten salt etching strategy to synthesize high-quality Ti₃C₂T_x MXene under relatively mild conditions [Fig. 10(a)]. By utilizing ZnCl₂ molten salt as a Lewis acidic medium at 550–600 °C, the Al layer in Ti₃AlC₂ MAX phase was selectively extracted, leading to the formation of Cl- and O-terminated Ti₃C₂T_x nanosheets with lateral sizes exceeding 10 μm. This approach effectively avoided fluorine contamination, improved structural stability, and yielded colloidal suspensions without additional intercalation steps. The resulting few-layer MXene films exhibited superior electrical transport characteristics, including a sheet resistance of ~4.5 Ω·sq⁻¹ at 90% optical transmittance and a work function tunable between 4.2–5.1 eV. Compared with conventional HF-based synthesis, the molten-salt route not only enhances safety and environmental compatibility but also enables controlled termination chemistry favorable for device integration. Such fluoride-free synthesis expands the applicability of MXenes in next-generation electronics, particularly in transparent conductors, low-power field-effect transistors, and stable interconnects, where high conductivity and environmental robustness are critical. Alhabeb et al. [140] developed a modified etching approach that replaces concentrated HF with an in situ HF-generating LiF/HCl solution, enabling safer and more controllable synthesis of Ti₃C₂T_x MXene [Fig. 10(b)]. In this method, Ti₃AlC₂ powders are immersed in an aqueous mixture of LiF and HCl, where Li⁺ ions intercalate simultaneously with the selective removal of Al, thereby promoting spontaneous delamination without additional ultrasonic treatment. The resulting Ti₃C₂T_x flakes exhibit larger lateral sizes (up to several micrometers) and improved colloidal stability compared to conventional HF-etched MXenes. Structural analyses revealed mixed −O, −OH, and −F terminations, which contribute to tunable surface chemistry and hydrophilicity. Films fabricated from these colloidal dispersions demonstrated uniform morphology, excellent processability, and high conductivity, with sheet resistances as low as ~5 Ω·sq⁻¹ at 90% optical transmittance. Beyond improved safety, this LiF/HCl route provides better control over intercalation chemistry and flake quality, thereby expanding the applicability of MXenes in scalable solution processing and device integration for next-generation electronic and energy technologies.

Pang et al. [141] recently introduced a universal HF-free electrochemical etching strategy for the rapid synthesis of MXenes under mild conditions [Fig. 10(c)]. By employing a carbon black/carbon fiber composite electrode and diluted HCl electrolyte with gentle heating, selective removal of the Al layer from Ti₂AlC was achieved at low bias voltages, producing Ti₂CT_x nanosheets with lateral sizes up to 25 μm and expanded interlayer spacing of 1.84 nm. This method was further extended to synthesize difficult MXene compositions such as V₂CT_x and Cr₂CT_x, which are otherwise inaccessible by conventional HF etching or molten-salt routes. The as-prepared MXenes exhibited flower-like architectures with high dispersibility in aqueous media and surface terminations dominated by −O/−OH groups. Functionally, the E-etched MXenes demonstrated remarkable electrocatalytic activity, showing overpotentials of ~570 mV for HER and further enhancement upon Co³⁺ ion decoration, with bifunctional HER/OER performance comparable to IrO₂-based catalysts. Moreover, Cr₂CT_x served as a stable cathode in aqueous Zn-ion batteries, delivering a capacity retention of 98% over 100 cycles and significant rate enhancement upon cycling. This HF-free approach not only overcomes the toxicity and safety limitations of HF-based synthesis but also provides a scalable and versatile route for fabricating diverse MXenes with multifunctional applications in catalysis and energy storage. Thakur et al. [142] recently demonstrated a theory-guided synthesis of a tungsten-based MXene, W₂TiC₂T_x, which represents one of the first MXenes derived from a non-MAX nanolaminated ternary carbide precursor [Fig. 10(d)]. By employing a modified (W,Ti)₄C_4−y precursor synthesized with excess aluminum to suppress oxygen incorporation and enhance vacancy formation in tungsten-rich layers, selective etching of covalently bonded tungsten planes was achieved under HF treatment, followed by TMAOH intercalation and delamination. The resulting W₂TiC₂T_x exhibited ordered out-of-plane tungsten–titanium stacking, large flake morphology, and stable colloidal dispersions. Structural and spectroscopic analyses confirmed mixed −O, −OH, and −F terminations, while STEM and SIMS revealed tungsten-rich basal planes with high structural integrity. Functionally, electrocatalysis, its electronic conductivity (~427 S·cm⁻¹) and distinctive optical absorption suggest potential for photonic and optoelectronic applications. This work establishes a pathway to synthesize stable tungsten-based MXenes from non-MAX precursors, thereby broadening the synthetic toolbox for 2D carbides and unlocking new chemistries for energy and electronic devices.

Despite these promising advances, the application of MXenes in semiconductor devices still faces significant challenges. Most MXenes are intrinsically metallic, and achieving stable semiconducting phases requires precise control of surface terminations, doping, or post-treatment, which remains difficult to scale. The coexistence of multiple surface functional groups makes it challenging to reproducibly tailor their bandgaps, while their susceptibility to oxidation and environmental degradation severely limits long-term device stability. Furthermore, large-area, high-quality semiconducting MXene films are still lacking, in contrast to the scalable growth of TMDCs via CVD or MBE. Finally, issues related to interface engineering, dielectric integration, and compatibility with BEOL processing must be carefully addressed before MXenes can be practically employed in post-Moore integrated circuits.

5 Contact engineering for 2D electronics

5.1 Making vdW contact between metals and 2D semiconductors

The electrical contact between the metal and channel is crucial for FET since it depends the contact resistance and thus influences the device performance such as the on/off ratio and the carrier mobility [143]. However, owing to the atomical thickness and dangling-bond-free surface of 2D semiconductor, the direct deposition of metals can result in the defects and damage to the 2D semiconductor channel, leading to higher contact resistance and thus degrade the FET performance [144]. Furthermore, the work function and the density of states of the contact materials also plays an important role [145, 146]. A metal with proper work function corresponding to the energy band of the semiconductor can reduce the Schottky barrier and lead to ohmic contact. To create clean and ohmic contact in 2D FET, methods such as vdW transfer electrode [147], high vacuum and low temperature evaporation [21], work function engineering [148], semimetal contact and doping [149, 150], have been developed.

In 2018, Liu et al. [144] adopted transferring metal films onto 2D semiconductors for resolving the defects caused by direct evaporation in contacts between 2D materials and electrodes. Instead of evaporating the metals on 2D materials that may cause damages and defects, they first deposited the metals on silicon substrates. These metal electrodes with atomically flat surface can be mechanically released from the silicon and be transferred onto the MoS₂ channel. As shown in Figs. 11(a)−(d), a clean and sharp interface was formed between the transferred Au and 2D semiconductor, while obvious defects were observed in evaporated Au/MoS₂ interface. Moreover, this transferred electrode method can avoid direct chemical bonding between metals and semiconductors. As illustrated in Fig. 11(e), the FET with evaporated Pt electrodes showed n-type conductivity, indicating a large n-type Schottky barrier. A p-type conductivity and ohmic contact were observed in FET with transferred Pt electrodes, which demonstrates the advantages of this approach [Fig. 11(f)]. In another work, 2D diodes with transferred electrodes showed performance close to the intrinsic exciton physics limit [147]. In recent, this method has been utilized to build wafer-scale 2D transistors and 3D integration of 2D semiconductors, indicating its potential in practical applications [151, 152]. Wang et al. [153] adopted soft metal In to form vdW contact with monolayer MoS₂ without chemical bonding. As revealed in Figs. 11(g, h), ideal interface was formed between In and MoS₂. FET fabricated by this technology shows low contact resistance (3.3 ± 0.3 kΩ·μm) and relative high mobility (167 ± 20 cm²·V⁻¹·s⁻¹) [Figs. 11(i, j)]. The soft nature of indium (In) enable the formation of high-quality interfaces with monolayer semiconductors and facilitate alloying with different metals to modulate the work function of electrodes, which helps reduce the contact resistance and adjust the polarity of 2D FETs.

In 2023, Kwon et al. [154] adopted an intercalation method to make clean vdW contact between electrodes and 2D semiconductors. As revealed in Fig. 11(k), before depositing Au on the semiconductor, they first deposited a Se layer. This Se layer can be moved by annealing in vacuum at 150 °C, resulting in a damage-free vdW contact between Au and the semiconductor. As illustrated in Fig. 11(l), the 2D FET with vdW Au contact showed p-type conductivity with on/off ratio above 10⁶ [Fig. 11(l)]. In addition to the aforementioned methodologies for constructing vdW contacts in 2D FETs, emerging research has focused on investigating interfacial interactions between vdW materials and 2D semiconductors [155, 156]. These transistors exhibit enhanced carrier mobility and low contact resistance, benefiting from the clean vdW metal-semiconductor interface.

5.2 Contact material engineering for 2D transistors

To reduce the Schottky barrier in metal-semiconductor contacts, electrodes with proper work functions should be considered in 2D metal-semiconductor contact. In addition of the work function, the formation of metal-induced gap states (MIGS) in the semiconductor bandgap arises from the penetration of metallic wave functions into the semiconductor, which hybridize with and perturb the intrinsic wave functions of the semiconductor. This phenomenon may also lead to the Fermi pinning and high contact resistance [Figs. 12(a, b)] [145, 157]. Different from metals, semimetals with nearly zero density of states can largely eliminate the MIGS [Fig. 12(c, d)]. To suppress the gap states at the interface of metals and 2D semiconductors, Shen et al. [145] adopted semimetal bismuth (Bi) as the contact electrodes in 2D FETs. As illustrated in Fig. 12(e), the FET with Bi electrodes shows higher on/off ratio than that of metal electrodes. Moreover, an ultralow contact resistance of ~ 123 Ω·μm was realized [Fig. 12(f)]. In 2023, Li et al. [21] utilized semimetal antimony (Sb) as electrodes for 2D FET. They found that the crystal direction of Sb played an important role in the contact between the electrode and the semiconductor. Compared to Sb (0001), Sb (01\stackrel{-}{1}2) exhibits stronger hybridization and vdW interaction with 2D semiconductors, enabling enhanced electron injection and achieving lower contact resistance approaching the quantum limit [Figs. 12(g, h)]. They realized a contact resistance as low as 42 Ω·μm [Figs. 12(i, j)]. Researchers also have demonstrated wafer-scale MoS₂ transistor arrays with exceptional performance, marking significant progress toward practical applications of 2D electronics. The development of p-type 2D transistors is critical for CMOS integrated circuits. Wang et al. [150] achieved p-type conduction in MoS₂- and WSe₂-based devices by selecting high-work-function metals like Pt and Pd. Through precise control of evaporation temperature and pressure, they established clean metal-semiconductor interfaces, minimizing damage typically induced by conventional deposition methods [Figs. 12(k, l)]. This approach yielded transistors with relatively low contact resistance (~3.3 kΩ·μm) and high hole mobility (~190 cm²·V⁻¹·s⁻¹). In 2024, Li et al. [148] synthesized composition-tunable VS_2xSe_2(1−x) (0 ≤ x ≤ 1) nanosheets through controlling the growth temperature via CVD [Fig. 12(m)]. These alloys exhibited composition-dependent surface potentials and work functions [from (4.79 ± 0.01) eV to (4.64 ± 0.01) eV]. The tunable work functions of 2D alloys can help reduce the Schottky barrier when contacting with different 2D semiconductors. Leveraging this tunability, they engineered heterostructures where VSe₂/WSe₂ combinations demonstrated robust p-type characteristics, while VS₂/MoS₂ configurations showed n-type behavior, as illustrated in their device schematics [Figs. 12(n, o)]. Despite this progress, the community remains divided on the dominant origin and strength of Fermi-level pinning in 2D contacts — whether it is primarily governed by MIGS at pristine interfaces or by defect-/dipole-mediated pinning at imperfect ones. Disentangling these contributions under realistic processing is essential, as it directly impacts how one prioritizes semimetal electrodes, transfer-assembled contacts, or work-function-tuned alloys in scaled devices [144, 145].

5.3 Interlayer mediated contacts for 2D devices

Traditional silicon-based contact engineering strategies like ion implantation and silicide buffer layers face challenges in atomically thin 2D semiconductors [158]. Jiang et al. [149] addressed this by developing a substitutional yttrium (Y) doping technique for few-layer MoS₂. As shown in Fig. 13(a), Their process involved plasma-induced sulfur vacancy generation followed by active metal Y deposition in a high vacuum (<1 × 10⁻⁸ torr) and annealing, which facilitated selective Y substitution at sulfur sites without excessive downward diffusion. The resulting Y-MoS₂ exhibited metallic behavior, enabling ohmic contacts with average contact resistance of 69 Ω μm, total resistance of 235 Ω·μm and ON-current density of 1.22 mA·μm^–1 for MoS₂ FETs [Figs. 13(b)–(e)]. Notably, they demonstrated scalable fabrication of large-area transistor arrays using this methodology. In a separate study, researchers introduced an intermediate conductive bridge layer incorporating gold-doped oxide interlayers [159]. First, a 20 nm-thick layer of low-work-function metals (Al, Ti, Cr, and Cu) was deposited via evaporation under vacuum conditions, followed by the sequential deposition of a 1 nm-thick Au layer. Subsequently, this metallic stack was intentionally exposed to ambient atmospheric conditions, leading to partial oxidation of the metal layer. The resulting oxide layer incorporated Au nanoclusters, forming a composite structure with heterogeneous work functions [Figs. 13(f)–(h)]. This engineered interface demonstrates enhanced compatibility for achieving optimal electrical contacts in 2D semiconductor devices, leveraging the work function tunability of the mixed metal-oxide system and the conductive pathways provided by the embedded Au nanocluster.

In summary, advanced contact engineering forms the foundation for high-performance 2D electronics. Current research has made remarkable progress on lowering the contact resistance through innovative approaches. 1D edge contact for 2D materials are also attractive for showing ultralow contact resistance and high carrier mobility [160−163]. However, for practical industrialization, future efforts should focus on developing scalable fabrication methods that maintain performance while ensuring compatibility with existing semiconductor manufacturing infrastructure and cost-effectiveness [164].

6 Applications of 2D transistors

As the feature sizes of semiconductor devices enter the sub-nanometer era, traditional silicon-based technology has encountered the dual challenges of physical limits and power consumption bottlenecks. 2D materials (such as graphene and transition metal sulfides) have become potential candidates for breaking through the limitations of Moore’s law, thanks to their atomic-level thickness, high carrier mobility, and surface characteristics without dangling bonds. However, efficiently integrating 2D materials into existing silicon-based processes still faces many challenges, especially in terms of large-area, low-damage, high-fidelity wafer-level transfer and heterostructure construction technology [105, 140, 153−158, 165−170].

6.1 Wafer-level integration of 2D materials and their heterostructures

2D materials have emerged as promising candidates for next-generation electronics due to their unique properties. However, challenges such as efficient transfer, interface engineering, and integration with existing semiconductor processes need to be addressed. This passage presents various innovative methods for wafer bonding, transfer, and integration of 2D materials to overcome these obstacles [140, 153, 154].

Traditional wet transfer relies on polymer carriers (such as PMMA), which can easily introduce residues and cause interface contamination. For example, PMMA residues significantly reduce the carrier mobility of graphene, while dry transfer faces issues of interlayer wrinkles and cracks. Figure 14(a) proposes a wafer bonding method based on BCB (bisbenzocyclobutene) adhesive, which transfers CVD-grown graphene and MoS₂ onto silicon wafers through a thermal pressing process. The hydroxyl-free nature of BCB avoids interface traps, and its thermoplasticity allows for repeated reshaping, supporting the construction of multilayer heterostructures (such as graphene/h-BN heterojunctions). This technology has successfully achieved uniform transfer of 4-inch wafers, with field-effect mobility as high as 4520 cm²·V⁻¹·s⁻¹, providing a compatibility solution for back-end integration [171]. Figure 14(b) has developed a transfer medium with a gradient surface energy modification (a three-layer structure: borate ester/PMMA/PDMS), which realizes the non-destructive release of graphene by adjusting the difference in surface energy. This method avoids polymer residues, improves the carrier mobility of graphene to 10⁴ cm²·V⁻¹·s⁻¹, and the surface roughness is below 1 nm. DFT calculations confirm that the low adsorption energy of borate ester reduces interface contamination, providing a high cleanliness transfer substrate for flexible electronic devices [172]. Figure 14(c) achieves thermally induced polymer deformation by adding volatile molecules (such as borneol), allowing 2D materials to form conformal contact with the target substrate. When transferring monocrystalline graphene grown on Cu foil to a PET flexible substrate, this method maintains atomic-level flatness and eliminates the need for polymer residues. Experiments show that the room temperature Hall mobility of graphene exceeds 142 000 cm²·V⁻¹·s⁻¹, and the quantum Hall effect is clearly visible at 1.7 K, verifying the interface quality [60].

In addition, lattice mismatch and differences in thermal expansion coefficients between 2D materials and target substrates can cause interface stress, affecting device performance. For example, the interface roughness of MoS₂ and SiO₂ introduces scattering centers, reducing carrier mobility. Semiconductor BEOL temperatures are typically below 400 °C, while high-temperature annealing of 2D semiconductors (such as MoS₂) can damage the underlying circuitry. How to achieve high-quality epitaxial growth at low temperatures is a key challenge. Figures 14(d) and (e) report the low-temperature integration of Bi₂O₂Se/Bi₂SeO₅ heterostructures. Through UV-assisted intercalation oxidation technology, Bi₂O₂Se nanosheets are partially oxidized into single-crystal Bi₂SeO₅, forming an atomically flat interface (interface roughness < 0.5 nm). This structure, as a high-κ gate dielectric, supports a subthreshold swing as low as 62 mV·dec⁻¹ for a 30 nm gate length transistor, with an electron mobility of 280 cm²·V⁻¹·s⁻¹, and multi-layer stacking is achieved through M3D (monolithic 3D) integration. Figure 14(e) further optimizes step-guided epitaxy, preparing vertical FinFET arrays with a channel width of only 1 nm, demonstrating the feasibility of high-density 3D integration [111, 161, 173]. Figure 14(f) realizes the parallel synthesis of multi-channel MoS₂ finFETs by controlling the step-flow growth of Cu foil. Combined with an ALD passivation layer, and logic gate circuits are constructed through hetero-integration, providing a hardware basis for multi-value computing [174].

Three-dimensional stacking requires high-density through-silicon vias (TSVs) and low-resistance interconnects, but existing TSV technology has issues with low alignment accuracy and high parasitic capacitance. Figure 14(g) shows an integrated circuit containing >10 000 2D TMD FETs and CMOS logic devices, achieving three-dimensional interconnection through TSV (through-silicon via) technology. Figure 14(h) applies Dual-Tier Design which Tier 1 consists of MoS₂ memtransistors (computing units), while Tier 2 incorporates graphene-based chemisensors (sensing units). The entire fabrication process operates below 200 °C ensuring compatibility with back-end-of-line (BEOL) integration. Non-volatile memory functionality is enabled by an Al₂O₃/HfO₂/Al₂O₃ floating-gate stack. The interconnect density achieved an interconnect density of 62 500 I/O per mm² , surpassing Intel’s Foveros (400 I/O/mm²) and hybrid bonding technologies (10 000 I/O/mm²) [175]. Figure 14(i) shows two-dimensional semiconductor materials (such as transition metal dichalcogenides, TMDs) can overcome the limitations of conventional silicon-based 3D integration, enabling the development of high-performance monolithic 3D (M3D) chips with single-crystalline structures. These methods offer solutions to key challenges in 2D material processing and integration, paving the way for their widespread application in advanced electronic devices [176].

Despite the significant progress made in the integration capabilities of 2D materials by the above technologies, the following challenges still exist: (i) Scalability of single-crystal growth: Epitaxially grown 2D materials are still limited to specific substrates (such as sapphire) and cannot be directly grown on the BEOL layer. (ii) Insufficient interface engineering: The Schottky barrier problem at metal-2D semiconductor contacts has not been fully resolved, restricting device performance. (iii) Thermal budget limitations: Material selection and process compatibility under low-temperature processes (<400 °C) still need optimization [155, 158, 177, 178].

Future research should focus on: Low-temperature epitaxial technology; Developing non-equilibrium growth processes (such as plasma-enhanced CVD) to break through temperature constraints; Interface reconstruction strategies: Utilizing ALD or MBE to achieve conformal coverage of ultra-thin high-κ dielectrics; Three-dimensional architecture innovation: Exploring the integration of vertical tunneling field-effect transistors (TFETs) and neuromorphic devices to promote the development of integrated memory and computing architectures [105, 157, 167, 179].

6.2 Next-generation ICs enabled by 2D materials

The advancement of three-dimensional heterogeneous integration (3DHI) and M3D technologies has emerged as a transformative pathway to overcome the limitations of conventional system-on-chip (SoC) scaling. By leveraging the unique properties of 2D materials, such as graphene [156], MoS₂, WSe₂, and h-BN, researchers have demonstrated groundbreaking architectures for vertically integrated logic [180, 181], memory, and sensing systems [182]. These innovations include high-yield transistor arrays [27], multifunctional 3D circuits, hybrid 2D-CMOS microchips [183], and neuromorphic hardware. This progress highlights the potential of 2D materials to redefine chip design, enabling ultra-dense integration, energy efficiency, and novel computing paradigms for artificial intelligence (AI) and machine vision applications [184−190].

traditional 3DHI faces challenges such as complex processing and intricate wiring. M3D integration presents a more efficient solution for chip connections. Large-area uniform 2D heterostructures were prepared using the layer-resolved splitting technique and the semi-dry transfer method, allowing for the monolithic stacking of 2D material-based transistors and memristors. As shown in Fig. 15(a), a six-layer 3D nanosystem was constructed to perform AI tasks, emulating the vertical heterogeneous integration of logic and memory. Conductive bridge random access memory was chosen to construct 2D material memristors, and their performance was enhanced by optimizing the double-layer structure WSe₂/h-BN/MoS₂ [191]. Figure 15(b) illustrates the construction of a 3D circuit using MoS₂, which exhibits multifunctional characteristics including logic, storage, and sensing. A 3D inverter has been realized, and the non-volatile storage capabilities and photosensing abilities of field-effect transistors have been demonstrated [192]. Figure 15(c), utilizing mass transfer printing (MTP) technology, was employed to construct MoS₂ field-effect transistor (FET) arrays with various architectures. The device yield of the back-gate MoS₂-FET arrays achieved 97.9%. Both top-gate and bottom-gate structures enhanced performance, with the bottom-gate MoS₂-FET arrays exhibiting performance comparable to that of state-of-the-art two-dimensional devices [190]. Figures 15(d) and (e) illustrate the process of transferring graphene onto a CMOS chip, which houses the readout circuit of an image sensor, via a back-end process. The graphene’s photoresponse relies on the photogating effect and is characterized by ultra-high gain, high responsivity, and low noise. It is capable of detecting light within the range of 300 to 2000 nm. The CMOS circuit handles signal processing and readout, confirming the viability of graphene for use in image sensors. Looking ahead, there is potential for enhancing resolution, broadening the wavelength detection range, and decreasing the size. As shown in Fig. 15(f), a 2 cm × 2 cm silicon microchip was designed and fabricated using the 180 nm CMOS technology node. Multilayer hexagonal boron nitride (h-BN) was integrated into the BEOL interconnections. The top electrodes and interconnections were fabricated through processes such as photolithography, etching, and metal deposition to form the 1T1M structure, thus preparing a high-integration-density 2D-CMOS hybrid microchip. The 1T1M cells can achieve an endurance of up to 2.5 million cycles, and their performance can be adjusted with different top electrode materials. The cells possess the spike-timing dependent plasticity (STDP) property, which was used to construct a spiking neural network (SNN) for handwritten digit classification, achieving an average accuracy of approximately 90%. Moreover, a CMOS circuit for an electronic neuron based on h-BN memristors was proposed. This study paves the way for the integration of 2D materials in microelectronics and memristive applications [193]. Figure 15(g) depicts a 3 × 3 imaging array with 27 detectors, designed and fabricated using a ~4-nm-thick WSe₂ crystal. This array is capable of performing two neural network functions: a classifier and an autoencoder. It boasts a processing speed of up to 20 million pixels per second and has a self-powering feature, consuming electrical energy solely during training. This ANN vision sensor is suitable for ultrafast recognition and encoding of optical images, offering a range of training options for ultrafast machine vision applications [194]. Figure 15(h) presents a 2D MoS₂-based reconfigurable analog hardware (RAH), which proposes a new direction for the development of general-purpose computing hardware. It offers a novel technical approach for the development of brain-inspired computing hardware and promotes the application of 2D materials in the field of general-purpose computing [195]. As shown in Fig. 15(i), high-density Au/h-BN/Au memristive crossbar arrays with high yield have been fabricated, which have great potential in ultra-low power neuromorphic hardware applications. This provides key technical support for the practical applications of 2D materials in high-density storage and other fields, and offers new directions and approaches to address the challenges faced by traditional computing hardware [196].

In conclusion, these studies on 2D materials encompass a broad spectrum of applications, ranging from 3D integration and image sensors to memristive devices, neural network-based imaging arrays, reconfigurable analog hardware, and high-density memristive crossbar arrays. They not only showcase the exceptional properties and vast potential of 2D materials but also offer significant technical support and new avenues for overcoming challenges in traditional computing hardware. These advancements are poised to play a pivotal role in the future evolution of microelectronics and related domains. By bridging the divide between material innovation and industrial fabrication, this work establishes a foundation for the next generation of electronics, providing scalable solutions to cater to the needs of AI, IoT, and beyond [166, 185, 197].

7 Conclusions and future prospects

The CMOS-based microelectronics industry has become an indispensable part of people’s daily lives. However, with the impending failure of Moore’s law, urgent technological innovations are needed to propel the continued advancement of the semiconductor industry. 2D materials, characterized by their ultra-thin thickness and unique physicochemical properties, have emerged as promising candidates for enabling further miniaturization of semiconductor devices in the post-Moore era. Currently, most methods for growing 2D materials suffer from either poor crystalline quality or insufficient area, hindering their industrialization. Therefore, synthesizing large-area, high-quality 2D semiconductor materials has become crucial. This review summarizes current methods for fabricating large-area high-quality 2D semiconductors, including substrate-induced growth, seeded epitaxial growth, and confined growth techniques. For industrialization, compatibility with existing CMOS BEOL is essential. We also discuss low-temperature synthesis strategies for achieving large-area 2D semiconductors. Nevertheless, competing hypotheses remain regarding the primary quality-limiting mechanism in low-temperature growth: some studies emphasize interfacial kinetics (e.g., adsorption/desorption and surface diffusion constraints at the substrate), whereas others point to strain-relaxation and defect formation under BEOL-compatible thermal budgets. Clarifying the relative contributions of these factors — especially for wafer-scale growth on insulating substrates — remains a key unresolved question for the field [87, 199]. Addressing the lack of suitable dielectric layers for 2D transistors, we review recent progress in synthesizing 2D dielectrics via CVD, PVD, and alternative approaches. Additionally, we summarize methods for improving metal-semiconductor contact interfaces, such as vdW contacts, contact engineering, and interlayer-mediated contacts in 2D devices. Finally, we explore various applications of 2D semiconductors in 3D integration and microelectronic technologies.

Although 2D semiconductor devices have demonstrated extraordinary potential in CMOS applications, completely replacing mature silicon-based processes remains a long-term challenge. Current commercial MOCVD and PECVD equipment are prohibitively expensive, and synthesizing high-quality, large-area 2D semiconductor materials incurs particularly high costs. Therefore, it is essential to reduce synthesis costs while further optimizing growth parameters to enhance efficiency and minimize waste generation. Although MOCVD is the most widely used method for low-temperature synthesis of two-dimensional semiconductors, the variety of materials producible via this approach remains limited. Expanding the range of metalorganic compounds and gases employed could enable the synthesis of more 2D semiconductor materials. Existing low-temperature CVD techniques often result in insufficient crystallinity and excessive defect densities within synthesized samples, necessitating improved fabrication processes to boost crystallinity and reduce defects. Methods such as seed epitaxy, substrate-induced epitaxy, and confinement growth face challenges where substrate size constraints limit the scalability of 2D semiconductor samples, underscoring the importance of developing high-quality wafer-scale substrates. High-temperature synthesis methods for 2D semiconductors remain incompatible with existing manufacturing infrastructure, requiring material transfer onto target substrates. However, current transfer technologies introduce organic residues and compromise sample integrity, adversely affecting device performance, thus demanding advancements in transfer processes. Deepening understanding of 2D material growth mechanisms and dynamics will be critical for enabling large-scale production of high-quality, large-area semiconductors in the future.

Although current 2D N-type MOSFETs exhibit exceptional performance, the development of high-performance P-type MOSFETs remains significantly lacking, necessitating researchers to explore and synthesize more advanced two-dimensional p-type semiconductor materials. Dielectrics are crucial for device functionality, yet the chemical inertness of 2D semiconductor materials poses substantial challenges for nucleation and uniform growth of high-κ dielectric layers on their surfaces. Ideal dielectric materials for 2D semiconductors must simultaneously possess high permittivity, chemical inertness, and stability [200, 201]. The application of 2D transistors in high-density integration demands enhanced yield, reliability, and stability, which requires minimizing defect densities at interfaces between 2D semiconductors and other materials [202]. Consequently, continuous optimization of metal electrode contact processes for 2D semiconductors is equally vital to fully realize their intrinsic performance capabilities. To address these persistent challenges in the field of 2D transistors, we should foster collaborative efforts across interdisciplinary research communities to accelerate the development of 2D transistor technologies. Only through collective coordination and innovation can we ultimately establish an optimal pathway to surpass Moore’s law, drive revolutionary breakthroughs in microelectronics, and meet the urgent demands of our data-intensive era.

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