Two-dimensional electronics in the post-Moore era: From fabrication to application

Abstract

As conventional semiconductor technologies encounter coupled limitations in dimensional scaling, energy efficiency, and functional integration, post-Moore electronics increasingly requires novel paradigms that unprecedentedly evolve integrated-circuit technology to propel the developments of computing, memory, sensing, and other emerging functions. Atomically thin two-dimensional (2D) materials exhibit excellent electronic and optoelectronic properties, positioning them as a compelling materials platform in the post-Moore era. However, the performance of devices based on 2D materials depends not only on their intrinsic properties, but also on material quality, interfacial configurations, as well as fabrication and integration methods. Accordingly, current research is shifting from exploring new materials toward investigating the entire progression from materials preparation and device fabrication to scalable application, which are mutually coupled and significant for pursuing intended functions. Clarifying the cross-scale relationships among these critical stages from fabrication to application is essential for advancing 2D materials from fundamental physical systems toward reliable post-Moore technologies.

Graphical abstract

Keywords

two-dimensional electronics / post-Moore era

Modern information science is driving rapidly increasing demands for computational throughput, integration density, energy efficiency, sensing capability, and hardware adaptability, whereas the continued miniaturization and optimization of conventional semiconductor devices are becoming progressively more constrained by short-channel effects, quantum confinement, interface scattering, and other fundamental limitations [1]. In this post-Moore context, two-dimensional (2D) materials, composed of strongly bonded atomic planes coupled by weak interlayer van der Waals (vdW) interactions, have emerged as promising candidates for future functional devices, owing to their lattice-defined atomic thicknesses and dangling-bond-free basal planes [2]. From the isolation of graphene in 2004 [3] through the demonstration of monolayer MoS₂ transistors in 2011 [4] to the formulation of van der Waals heterostructures in 2013 [5], decades of intensive research have positioned 2D materials at a pivotal juncture of transitioning from fundamental laboratory discoveries toward practical integration in post-Moore microelectronics. The 2D materials family has now expanded considerably to encompass a diverse range [Fig. 1(a)] with various electrical properties [Fig. 1(b)], fulfilling the demands for channels, dielectrics, and active layers, while representative 2D transistors, photodetectors, and memories have demonstrated comparable or even superior performance to conventional devices [6]. The research priority has shifted from whether a specific 2D material or device can exhibit exceptional properties to how those properties can be preserved through successive processing steps with high uniformity and reproducibility. Therefore, the advancement of 2D electronics necessitates application-driven strategies including materials preparation, device fabrication, and scalable integration, making the progression from fabrication to application a framework for identifying the critical conditions for intrinsic capabilities ultimately being converted into dependable electronic technologies.

For practical applications, neither the appealing properties of 2D materials nor the exceptional performance demonstrated by individual devices can reflect the eventual performance, since characteristics may further be modified or eliminated during subsequent fabrication, scalable integration, and practical operation. Specifically, at the material-preparation stage, advances in epitaxial and vapor-phase synthesis have extended 2D crystals from exfoliated flakes to large-area films, which allow material characteristics to be regulated during growth, where cutting-edge research emphasizes further advances in wafer-level uniformity, reproducibility, and preservation. At the device-fabrication stage, mechanical transfer allows separately optimized materials to be combined through designed vdW interfaces and is consequently suitable for constructing high-performance devices, whereas direct growth and deposition are more amenable to large-area construction but may alter material properties under the thermal and chemical conditions during integration. At the scalable application stage, the construction route shows a performance–scalability trade-off between obtaining high performance and achieving scalability, uniformity, and reproducibility, where optimal balance in these competing objectives is inherently determined by application-specific functional requirements. Consequently, a series of recent publications in Frontiers of Physics, which span controlled materials synthesis, functional device construction, and application-oriented demonstrations (Fig. 2), provides a timely and representative basis for assessing the transition from fabrication to application, while also clarifying that these stages are mutually coupled and cannot be optimized independently.

As the foundation of 2D electronics, material preparation aims to acquire desired electronic states and scalability required for targeted functions, by establishing carrier polarity, defect populations, and chemical reactivity as controllable dimensions during synthesis. This principle is illustrated by recent studies in which growth variables were linked explicitly to polarity, defect chemistry, or downstream transformation. Peng et al. [9] demonstrated that large-area growth and carrier-polarity control can be integrated within a unified synthesis strategy by employing vanadium-assisted epitaxy to regulate both domain alignment and dopant incorporation, producing centimeter-scale p-type monolayer MoS₂ with high hole mobility. Pan et al. [10] demonstrated that defects introduced during growth can directly influence subsequent device functionality by controlling sulfur-vacancy populations through the sulfur-vapor environment during CVD, thereby clarifying their influence on carrier recombination and photoresponse in p-Si/MoS₂ self-powered photodetectors. Chu et al. [11] demonstrated that material synthesis can be designed in anticipation of subsequent functional transformation by regulating precursor delivery during the CVD growth of 2D HfSe₂, enabling its controlled oxidation into HfO₂/HfSe₂ heterostructures. Collectively, these studies establish that 2D-material quality is not a single structural metric, but a function-dependent combination of crystallographic, electronic, and chemical attributes. Future progress therefore requires a predictive and application-oriented synthesis paradigm that connects growth mechanisms to functional response, as well as controls the uniformity at the wafer scale.

Subsequently, 2D functional devices must be constructed by integrating 2D materials with dielectrics, electrodes, substrates, encapsulation layers, and other semiconducting or ferroic materials, thereby escalating the challenge from controlling an individual crystal to controlling a sequence of assembled interfaces. For example, when 2D materials are employed as channels in FETs, their atomically thin nature enables strong electrostatic control, while the absence of surface dangling bonds suppresses surface-state formation and associated carrier scattering. However, the same surface characteristics also hinder their integration with gate dielectrics, since chemically inert surfaces lack active sites for uniform nucleation and controllable interfacial bonding. Mechanical transfer offers a nondestructive route for integrating dielectrics onto 2D channels, but its low processing throughput impedes wafer-scale implementation, whereas conventional adhesion-promoting treatments can compromise channel quality by intensifying carrier scattering and thereby diminishing the intrinsic advantages of 2D channels. He et al. [12] systematized this integration dilemma by classifying interface-formation routes as top-down or bottom-up and interfaces as vdW or quasi-vdW, thereby relating interface quality and fabrication compatibility to how the constituent materials are combined. By physically separating the preparation of constituent materials from their integration, top-down assembly can preserve intrinsic material properties and induce high device performance, but it remains limited by transfer yield, alignment accuracy, and assembly throughput. Conversely, bottom-up routes offer a more direct path toward CMOS-compatible scaling but may degrade materials already present in the stack; hybrid or novel routes therefore become necessary when neither performance nor scalability can be achieved through a single approach. This framework also encompasses the HfSe₂-to-HfO₂/HfSe₂ conversion reported by Chu et al. [11], in which controlled oxidation transforms part of a parent crystal into a functional oxide/semiconductor stack; the direct vdW epitaxy of ultrathin CsPbI₃ on transition-metal dichalcogenides reported by Lu et al. [13], in which relaxed lattice-matching requirements facilitate the formation of a type-II optoelectronic interface; and the few-layer MoTe₂/CdS₀.₄₂Se₀.₅₈ heterojunction reported by Ma et al. [14], in which CVD-grown alloy flakes were combined with mechanically exfoliated MoTe₂ through dry transfer. Moreover, the carrier-injection interface can redefine the electronic state of an atomically thin channel during contact integration and thereby negate improvements previously achieved through dielectric or heterostructure engineering. Device formation should therefore be treated as the co-design of the complete material stack and fabrication sequence, with progress judged by whether the required properties can be preserved through the coordinated optimization of multiple interfaces and ultimately expressed as stable and reproducible device operation.

Towards scalable application, logic, memory, and photodetection provide three representative functional domains for evaluating 2D electronics, as they include complementary capabilities in charge transport, state retention, and light-to-electrical conversion. Logic electronics seeks to maintain electrostatic control and drive capability as channel lengths and operating voltages continue to decrease. In this context, He et al. [12] reviewed the progress and opportunities associated with FET structures, while specific quantum-transport calculations by Li et al. [15] predicted that sub-5-nm bilayer GaSe MOSFETs can deliver ultrahigh on-state current. These studies provide a benchmark for post-Moore scaling and emphasize the significance of preserving the predicted transport behavior and device variability over dielectric integration. Compared with logic devices, memory electronics place greater emphasis on controllable and persistent state switching rather than carrier mobility and electrostatic control, aiming to support the writing, retaining, and erasing of information. Guided by this requirement, recent studies demonstrate complementary routes toward this objective, where room-temperature ferroelectricity in ultrathin vdW SnP₂S₆ enables polarization-controlled modulation of a 2D channel [16], the converted HfO₂/HfSe₂ incorporates interfacial ion dynamics into a functional memory stack [11], and the review by Niu et al. [17] situates such switching mechanisms within broader device architectures and arrays. These works indicate that 2D memory should be evaluated not merely by polarization or resistive switching behavior, but by coordinating material, interface, and device design into controllable, persistent, and scalable information storage ability. Photodetection establishes a priority on efficiency of converting absorbed photons into carriers with minimal external power, where band alignment, interfacial recombination and optical absorption are consequential. Accordingly, Meng et al. [18] demonstrated the importance of built-in fields and carrier dynamics by constructing self-powered transition-metal-dichalcogenide photodetectors, while the defect-regulated p-Si/MoS₂ junction [10], directly grown CsPbI₃/TMDC interface [13], and transferred MoTe₂/CdS_0.42Se_0.58 heterojunction [14] demonstrate the effects of growth control, bottom-up epitaxy, and top-down assembly, respectively, to efficient carrier separation. Across these applications, the central insight is that device function is not a direct extension of any isolated material property, but an emergent consequence of how intrinsic states, interfacial interactions, and device architectures are organized across multiple scales, which provides an instructional path from fabrication to application.

In summary, the transition of 2D materials from fundamental research to practical post-Moore technologies requires more than exceptional material properties or device performance. It therefore depends on cross-scale co-design in which synthesis establishes the required material states, interface engineering preserves and couples those states within complete device architectures, and scalable integration translates them into reproducible functionality. More fundamentally, application is the very organizing principle that defines which material capabilities must be created, how interfaces should be constructed, and how 2D components should be integrated with established semiconductor platforms to enable functions as computing, memory, sensing, and heterogeneous architectures that are difficult to realize using conventional materials alone.

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