IGZO-based capacitorless 2T0C DRAM operation at 77 K for cryogenic computing

Abstract

In this work, an IGZO (In−Ga−Zn−O) 2T0C DRAM (dynamic random access memory) is demonstrated as a cryogenic memory as low as 77 K. The effects of temperature on the IGZO TFTs electrical properties are investigated. We observe that the subthreshold swing (SS) is improved from 161 to 99 mV/dec with no penalty of on-state current (I_ON) @V_TH+1 V reduction when temperature decreased from 300 to 77 K. More importantly, the corresponding V_TH shift positively from −1 to 0.5 V, indicating a transition from depletion-mode to enhancement-mode of IGZO TFTs, which is crucial for the low power operation and data retention time (DRT) optimization. By integrating this IGZO TFT to 2T0C DRAM, the retention time of the DRAM cell is significantly enhanced to 8000 s at 77 K, more than 5 times longer than the one at 300 K. The optimized data retention time also results from the lower leakage current (6 × 10⁻¹⁸ A/μm) of at 77 K due to the suppress of carriers thermally excitation and tunneling in IGZO channel at cryogenic temperature. Additionally, a large read current margin (I_data‘1’/I_data‘0’) of approximately 10³ is achieved across wide temperature range. This study demonstrates the potential of IGZO 2T0C DRAM cells for future cryogenic computing systems.

Graphical abstract

Keywords

In−Ga−Zn−O (IGZO) / DRAM (dynamic random access memory) / capacitorless 2T0C / cryogenic memory

1 Introduction

Cryogenic computing system like quantum computing holds promise for pushing the boundaries of computing capabilities by leveraging the unique physical properties of qubits, such as entanglement and superposition [1], attracting greatly attention for its faster computing speed and low power consumption. But the development of quantum system face some challenges. A large amount of memory is required to store programs and data generated during the quantum error correction [2]. Moreover, the qubits need to operate at extremely low temperature [3, 4], thus, the entire quantum system including memory system like DRAM (dynamic random access memory) should be able to work at cryogenic temperature (typically considered to be 77 K by liquid nitrogen cooling, which is currently the most suitable cooling temperature for cryogenic memory considering the reduction of heat transfer and refrigeration costs). Currently, there already has some studies on the cryogenic characteristics of silicon-based capacitorless DRAM [5, 6]. However, the relative short retention time even at cryogenic temperature (ms level) poses a serious challenge to Si-based DRAM [7]. The increased power consumption resulting from frequent refresh cycles remains significant in quantum computing systems.

In−Ga−Zn−O (IGZO) semiconductor exhibit two critical technological advantages: (i) Back end of line (BEOL) compatibility enabled by low-temperature deposition process (<400 °C); (ii) ultra-low off-state currents (<10⁻¹⁹ A/μm) derived from a wide bandgap (~3.5 eV). Based on these advantages, IGZO TFTs can achieve high-density integration [8−15] and the capacitorless 2T0C DRAM based on IGZO with ultra-low off-state current can achieve long DRT (several hours) which can reduce the power consumption in less refresh cycle [16−25]. These properties can be further improved at cryogenic temperatures. In this way, IGZO-based 2T0C DRAM can become one of the completive candidates as cryogenic memory. Besides, IGZO’s cryogenic transport is governed by disorder-induced localization, contrasting with the band-like conduction in crystalline oxides. This makes IGZO suitable for applications requiring low leakage currents and uniform thin films, while crystalline oxides excel in high-mobility, high-frequency devices. Future work should explore defect engineering in IGZO to mitigate low-T localization while retaining its amorphous advantages.

This work systematically investigates the IGZO 2T0C DRAM as cryogenic memory, providing critical insights for cryogenic memory system design. Our results exhibit the temperature-induced phenomena in IGZO TFTs: a decrease in on-stage current (I_ON), leakage current (I_leak) and subthreshold swing (SS) at lower temperatures, and a positive threshold voltage (V_TH) shift under cryogenic conditions. Capitalizing on the remarkable I_leak decrease and positive V_TH observed at 77 K, we demonstrate an enhancement in memory retention capabilities. The 2T0C DRAM cell achieves an extended retention time exceeding 8000 s at 77 K − representing a 5-times improvement compared with room-temperature operation. This highlights the substantial potential of cryogenically operated IGZO-based memory systems for low-power, long-retention cryogenic memory applications.

2 Device fabrication

The fabrication process flow of the 2T0C memory cells is illustrated in Fig.1(a). Firstly, a 20-nm-thick Mo layer was sputter-deposited on a cleaned SiO₂/Si substrate and patterned into the storage node contact and write-word-line (WWL) regions via inductively coupled plasma (ICP) dry etching. Subsequently, a 10 nm Al₂O₃ layer was deposited by atomic layer deposition (ALD) at 300 °C. Following this, a 5 nm IGZO channel layer was formed by magnetron sputtering and patterned using a diluted HNO₃ wet etching process. The source/drain regions were then defined, and electrode metals (20 nm Ni/20 nm Au) were deposited by electron-beam evaporation (EBE) followed by a lift-off process. A dual-layer passivation structure consisting of 2 nm Al₂O₃ and 8 nm HfO₂ was sequentially deposited by ALD at 200 °C. Finally, interconnect windows were opened through ICP dry etching, and interconnect metals (20 nm Ni/20 nm Au) were deposited to complete the device. The circuit schematic and optical micrographs of the DRAM cells are presented in Fig.1(b, c), respectively, with a channel length of 1.2 μm and width of 10 μm. As shown in the schematic, the gate of the read transistor serves as the storage node, enabling data storage during the write operation. The memory states can be distinguished by monitoring the readout current as a function of the V_SN. It is noteworthy that the gradual decrease in V_SN, primarily caused by charge leakage through off-state leakage currents, directly governs the transition between memory states and may ultimately lead to data retention failure.

3 Result and discussion

In order to investigate the cryogenic characteristics of IGZO TFTs, we carry out low-temperature electrical characterization measurement of IGZO TFTs. Fig.2(a) shows the temperature-dependent (from 300 K down to 77 K) transfer characteristic with channel length (L_CH) of 1.2 μm and channel width (W_CH) of 10 μm at V_DS = 0.1 V. Extracted SS in Fig.2(b) shows an enhancement from 161 mV/dec at 300 K to 99 mV/dec at 77 K. The SS is extracted according to the formula: SS = dV_GS/dlog(I_DS) across at least two decades current. When temperature decreases, the enhancement of SS is due to the energy required for charge carriers to overcome the potential barrier k_BT decreases followed by the equation:

(1)SS={\displaystyle \frac{k_{\mathrm{B}}T}{q}}\mathrm{l}\mathrm{n}\left(10\right) \left(1+{\displaystyle \frac{C_{\mathrm{s}}+C_{\mathrm{i}\mathrm{t}}}{C_{\mathrm{o}\mathrm{x}}}}\right),

where k_B is the Boltzmann constant, T the temperature, q the electron charge and C_s, C_it, C_ox the channel, D_it-induced, gate oxide capacitances, respectively. With the improved SS at cryogenic temperature, 2T0C DRAM can achieve an optimized read-out operation with a larger data margin and faster read speed. Fig.2(c) plots the extracted V_TH as a function of operating temperature show that V_TH shift positively from −1 to 0.5 V with temperature from 300 K down to 77 K. The V_TH is defined as V_GS satisfying I_DS = 100 pA × (W_CH/L_CH) [24]. The positive V_TH at cryogenic temperature can be explained that fewer free electrons generated from the carrier thermal excitation. In detail, when the temperature drops from 300 to 77 K, the thermal energy of the electrons (k_BT) decreases significantly, causing the electrons to be more concentrated in localized states with energy lower than the conduction band bottom rather than in free states. On the other hand, the free electron concentration (η) in the conduction band decreases exponentially with temperature called carrier freeze-out, and a higher gate voltage is required to accumulate enough electrons to form a conductive channel, which leads to a positive threshold voltage shift. A positive threshold voltage indicates an enhancement-mode operation in IGZO TFTs which by keeping the data at zero hold voltage with lower leakage [25]. In detail, the enhancement-mode write transistor with positive V_TH can achieve smaller off-current compare to write transistor with negative V_TH at same holding voltage. In this case, enhancement-mode IGZO TFTs at cryogenic temperature can preserve the charge for a much longer time beneficial from the lower leakage, thus, improving the data retention time.

We observed that the drain current (I_DS) is influenced by thermally activated carriers. To represent this temperature dependence, the drain current can be expressed as an exponential dependence with the inverse of temperature:

(2)I_{\mathrm{D}\mathrm{S}}=I_{\mathrm{D}\mathrm{S}0}\times \mathrm{e}\mathrm{x}\mathrm{p}\left({\displaystyle \frac{-E_{\mathrm{a}}}{k_{\mathrm{B}}T}}\right),

where E_a is the activation energy describing the energy required to release an electron from the localized states related to temperature. To verify if above Eq. (2) is accomplished in these devices, ln(I_DS) vs. 1/(k_BT) curves at V_DS = 0.1 V and V_GS from −0.5 to 2.5 V were plotted in Fig.3(a). To extract E_a, Eq. (1) can be turned into

(3)\mathrm{l}\mathrm{n}{I}_{\mathrm{D}\mathrm{S}}=\mathrm{l}\mathrm{n}{I}_{\mathrm{D}\mathrm{S}0}-{\displaystyle \frac{E_{\mathrm{a}}}{k_{\mathrm{B}}T}} ,

where E_a can be extracted from the slope of the fitting line in Fig.3(a). The extracted E_a vs. V_GS at V_DS = 0.1 V is presented in Fig.3(b). In the subthreshold region, the current is greatly affected by temperature, and the carrier activation mechanism is primarily thermal activation and hopping with a higher E_a of 0.2 eV. By applying a higher V_GS, the Fermi level is close to or entering the conduction band, and the activation energy is equal to E_C−E_F, which is close to zero. This transition from carriers thermally excitation and hopping to conduction band transport can be clearly observed in Fig.3(b) and the transition point is closed to 0 V. The relatively small E_a of 0.2 eV in subthreshold region compared to the previous work (0.3−0.6 eV) [26] usually reflects fewer material defect states or energy levels in IGZO films, indicating the higher film quality which can contribute to the cell optimized.

The corresponding output characteristics at operating temperature of 300, 200 and 77 K are shown in Fig.4(a)−(c), respectively. The output curves exhibit ohmic contacts in the linear region and saturation characteristics can be observed at relative higher V_DS region even the operating temperature down to 77 K. Due to factors such as decrease in carrier mobility, V_TH positive shift, and decrease in thermally excited carrier concentration, I_DS decreased from 12.8 to 4.4 μA/μm at V_DS = 1 V and V_GS = 2 V. It should be noted that although the current of IGZO TFTs decrease to 4.4 μA/μm at 77 K, it still meets the requirements for driving the IGZO 2TOC cell [27].

In order to further describe the temperature-dependent mechanism of leakage current in IGZO transistors, Fig.5(a, b) plot band diagram in S/D direction showing the possible mechanisms for IGZO TFTs operated in sub-threshold region at 300 and 77 K. There are several reasons for the I_leak decrease at cryogenic temperature: (i) electrons thermal excitation in shallow-level defects, (ii) electrons directedly tunneling, and (iii) trap-assisted tunneling. These effects result in fewer carriers being generated at cryogenic temperatures, leading to a reduction in leakage current. Fig.5(c, d) plot a band diagram in metal-insulator-semiconductor (MIS) structure explaining the above mechanisms. In details, thermally activated and tunneling carriers always populate the states within 2k_BT region energetically with respect to the Fermi level determined fundamentally by the Fermi−Dirac (FD) distributions. When cooling down the device from T = 300 to 77 K, less mobile electrons that possibly contribute to I_leak could be expected, leading to much lower I_leak at the subthreshold regime (V_GS<V_TH), and with consequent longer retention time.

To experimentally investigated the leakage characteristics of IGZO TFTs under cryogenic temperature, the retention characteristics of IGZO 2T0C are tested at temperature down to 77 K. Fig.6(a) exhibits the measurement setup of write and read operations for 2T0C cells. In the write stage, WWL is set at high voltage of 3 V to turn on the write transistor and BL is set at 1/0 V for writing data ‘1’/data ‘0’ . In the read stage, WWL and BL is set at low voltage of 0 and 0.1 V to keep the off-state and minimize the leakage current which is important for the retention characteristic. Fig.6(b, c) show the data ‘1’/data ‘0’ retention characteristic of IGZO TFTs-based DRAM cell measured at 300, 200 and 77 K with 0.1 V V_SN drop. The retention time of data ‘1’ at 200 and 77 K increase to approximately 5000 and 8000 s, respectively, compared to the one of ~1500 s at room temperature, as shown in Fig.7(a). The off-state leakage current can be calculated using the formula: I_leak = 0.1 V × C_SN/t_ret and is about 6 × 10⁻¹⁸ A/μm at 77 K with storage capacitance of 5 pF, which can be further reduced by improving device structures such as overlap areas and device scaling. The retention characteristics of data ‘0’ show the same trend. The storage node voltage V_SN of DRAM cell are extracted from transfer curves fitting. Noted that the leakage current I_leak refer in this article consists of off-stage current of write transistor I_DS-OFF-TW and gate leakage of read transistor I_GS-TR (I_leak = I_DS-OFF-TW + I_GS-TR). But in long-channel devices, due to the relatively large EOT of gate oxide layer, the gate leakage I_GS-TR is much smaller than I_DS-OFF-TW. Therefore, we can consider that I_leak ≈ I_DS-OFF-TW. The reduction in leakage current under cryogenic conditions can be attributed to three primary mechanisms: diminished thermal excitation of electrons in shallow-level defects, suppressed direct tunneling of charge carriers, and reduced probability of trap-mediated tunneling processes. Collectively, these phenomena limit carrier generation at low temperatures, thereby effectively mitigating current leakage. On the other hand, the energy required for electrons to overcome the oxide layer potential barrier is more difficult to obtain through thermal fluctuations at cryogenic temperatures, and the tunneling probability decreases exponentially, leading to a reduction in gate leakage I_GS-TR. Fig.7(b) shows read-out current and current ratio as a function of operating temperature, demonstrating a large read margin of 10³. The read-out current of both data ‘1’ and data ‘0’ decrease as the temperature falling follow the transfer characteristic. Finally, the performance benchmark of representative temperature dependent 2T0C DRAM cells is summarized in Fig.7(c) and Tab.1, showing obvious advantages of our IGZO 2T0C DRAM bit-cell. To our best knowledge, this work presents first comprehensive experimentally investigation of cryogenic 2T0C DRAM based on the oxide channels. There exist no other similar research on cryogenic oxide channel-based 2T0C DRAM.

4 Conclusion

An IGZO-based 2T0C DRAM cell has been investigated as a cryogenic memory cell for cryogenic computing systems design. The transfer characteristics of IGZO TFTs exhibit that I_ON, SS decreases and V_TH shifts positively with temperature decrease. The retention properties are significantly enhanced as the temperature decreases, achieving a leakage current as low as 6 × 10⁻¹⁸ A/μm at 77 K and a retention time exceeding 8000 s. These results demonstrate the potential of IGZO-based memory for future cryogenic memory systems in quantum computing and other low-temperature applications.

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