An effective fault localization approach for Verilog based on enhanced contexts
Zhuo ZHANG, Ya LI, Lei XIA, Jianxin XUE, Jiang WU, Xiaoguang MAO
An effective fault localization approach for Verilog based on enhanced contexts
[1] |
Flake P, Moorby P, Golson S, Salz A, Davidmann S . Verilog HDL and its ancestors and descendants. Proceedings of the ACM on Programming Languages, 2020, 4( HOPL): 87
|
[2] |
Foster H D. Trends in functional verification: a 2014 industry study. In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference. 2015, 1−6
|
[3] |
Kuon I, Rose J . Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26( 2): 203–215
|
[4] |
Foster H. The 2020 Wilson research group functional verification study. See Blogs.sw.siemens.com/verificationhorizons/2020/11/10/part-2-the-2020-wilson-research-group-functional-verification-study website, 2020
|
[5] |
Agha G, Palmskog K . A survey of statistical model checking. ACM Transactions on Modeling and Computer Simulation, 2018, 28( 1): 6
|
[6] |
Huang S Y, Cheng K T, Chen K C, Lu J Y J. Fault-simulation based design error diagnosis for sequential circuits. In: Proceedings of 1998 Design and Automation Conference. 1998, 632−637
|
[7] |
Mahzoon A, Große D, Drechsler R. Combining symbolic computer algebra and Boolean satisfiability for automatic debugging and fixing of complex multipliers. In: Proceedings of 2018 IEEE Computer Society Annual Symposium on VLSI. 2018, 351−356
|
[8] |
Wong W E, Gao R, Li Y, Abreu R, Wotawa F . A survey on software fault localization. IEEE Transactions on Software Engineering, 2016, 42( 8): 707–740
|
[9] |
Jiang T Y, Liu C N J, Jou J Y. Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. In: Proceedings of 2005 IEEE International Symposium on Circuits and Systems. 2005, 5682−5685
|
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