Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

Abstract

A 1 kbit antifuse one time programmable (OTP) memory IP, which is one of the non-volatile memory IPs, was designed and used for power management integrated circuits (ICs). A conventional antifuse OTP cell using a single positive program voltage (V_PP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time, securing the reliability of medium voltage (V_M) devices that are thick gate transistors. A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop. For the newly proposed cell, a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse. The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek’s 0.18 μm Bipolar-CMOS-DMOS (BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.

Keywords

one time programmable memory IP / antifuse / hard breakdown / dual program voltage / post-program resistance

References

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