Structure and design method for pulse-triggered flip-flops at switch level

Abstract

A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed, which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are needed to eliminate the switching activities of internal nodes. Based on the proposed structure and design technique, two pulsed flip-flops were implemented and simulated. The proposed pulsed flip-flops have simple circuit structures. HSPICE simulation shows that the proposed pulsed D flip-flop outperforms the conventional pulsed D flip-flop by 17.2% in delay and 30.1% in power-delay-product (PDP) and the proposed pulsed JK flip-flop has low power and small PDP compared with pulsed D pulsed flip-flops, confirming that the proposed structure and design technique are simple and practical.

Keywords

flip-flop / pulse-triggered / transmission voltage-switch theory / low power

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