LK−MVS joint modeling for NCFET circuit robustness and digital decoder delay variation analysis

Abstract

Timing variability induced by device manufacturing fluctuations has become a pervasive and critical challenge for low-voltage logic circuits, which severely impairs the timing margin and operational accuracy of core peripheral circuits such as decoders. In sub-1-V low-voltage applications, gate-level delay discretization in decoders will be magnified into wordline arrival-time mismatches, posing insurmountable obstacles to the realization of low-power and high-reliability integrated systems. To address this issue, this paper proposes a closed-loop paradigm integrating device modeling-circuit implementation-robustness evaluation-feedback design for ferroelectric negative-capacitance field-effect transistors (NCFETs) in low-voltage logic applications. First, under a strict charge-conservation framework, the Landau-Khalatnikov (LK) ferroelectric dynamics is coupled with the MIT virtual-source (MVS) channel conduction model to construct a simulation program with integrated circuit emphasis (SPICE)-compatible compact model for NCFETs that can characterize device-to-device (DTD) variations. Second, DTD variations are explicitly introduced to simulate process fluctuations in ferroelectric layer thickness (t_FE), and the resulting statistical perturbations are propagated from the device level to the gate-level 2−to−4 decoder circuit. Finally, with the 2−to−4 decoder as a case study, the propagation delays of all output signals are quantified, and a “DTD-centric” feedback path aimed at design-window convergence is formulated. The results show that within a process window of approximately t_FE ≈ 10 nm, the proposed model successfully reproduces experimentally comparable I−V characteristics; the NCFET-based 2−to−4 decoder maintains correct functionality under low voltage drain drain V_DD, and the coefficient of variation (C_V) of its propagation delay is controlled within 3%–7%, exhibiting a substantial design optimization window for low-voltage logic design.

Keywords

Compact model / Decoder circuit / Device-to-device (DTD) variations / Design optimization window / Ferroelectric dynamics / Ferroelectric negative-capacitance field-effect transistors (NCFET) / Low-voltage design

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