Device Physics and Architecture Advances in Tunnel Field-Effect Transistors

Abstract

The persistent pursuit of miniaturization and energy efficiency in semiconductor technology has driven the scaling of complementary metal-oxide-semiconductor field-effect transistors (CMOS FETs, i.e., the MOSFETs) to their physical limits. Conventional MOSFETs face intrinsic challenges, especially the Boltzmann limit that imposes a fundamental lower bound on the subthreshold swing (SS ≥ 60 mV dec⁻¹ at room temperature). This limitation severely restricts voltage scaling and exacerbates static power dissipation. To overcome these bottlenecks, tunnel field-effect transistors (TFETs) have emerged as a promising post-CMOS alternative. The advantages of ultra-small SS well below the Boltzmann limit, as well as ultralow leakage currents, make TFETs ideal for low-power electronics and energy-efficient computing in the future information industry. However, its current development has encountered significant resistance to further performance improvement requirements; new breakthroughs have evolved to be based on interdisciplinary research that covers materials science, device technology, theoretical physics, and so on. Here, we provide a review on the design and development of TFET, which mainly describes the device physics model of tunnel junctions, and discusses the optimization direction of key parameters, the design direction of potential structures, and the development direction of the innovation system based on the device physics. Also, we visualize the framework for the figures of merit of TFET performance and further forecast the future applications of TFET.

Keywords

beyond CMOS devices / subthreshold swing device physics / three-dimensional nanowire / tunnel field-effect transistor / two-dimensional material / van der Waals heterostructure

References

[1] M. M. Waldrop, “The Chips Are Down for Moore's Law,” Nature 530, no. 7589 (2016): 144-147.

[2] International Roadmap for Devices and Systems (IRDS™) 2023 Update (IEEE, 2023), https://irds.ieee.org/editions/2023.

[3] S. Cristoloveanu, J. Wan, and A. Zaslavsky, “A Review of Sharp-Switching Devices for Ultra-Low Power Applications,” IEEE Journal of the Electron Devices Society 4, no. 5 (2016): 215-226.

[4] D. E. Nikonov and I. A. Young, “Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking,” Proceedings of the IEEE 101, no. 12 (2013): 2498-2533.

[5] E. O. Kane, “Zener Tunneling in Semiconductors,” Journal of Physics and Chemistry of Solids 12, no. 2 (1960): 181-188.

[6] M. Luisier and G. Klimeck, “Simulation of Nanowire Tunneling Transistors: From the Wentzel-Kramers-Brillouin Approximation to Full-Band Phonon-Assisted Tunneling,” Journal of Applied Physics 107, no. 8 (2010): 084507.

[7] J. Appenzeller, Y. M. Lin, J. Knoch, and P. Avouris, “Band-To-Band Tunneling in Carbon Nanotube Field-Effect Transistors,” Physical Review Letters 93, no. 19 (2004): 196805.

[8] H. Lu and A. Seabaugh, “Tunnel Field-Effect Transistors: State-Of-The-Art,” IEEE Journal of the Electron Devices Society 2, no. 4 (2014): 44-49.

[9] A. M. Ionescu and H. Riel, “Tunnel Field-Effect Transistors as Energy-Efficient Electronic Switches,” Nature 479, no. 7373 (2011): 329-337.

[10] U. E. Avci, D. H. Morris, and I. A. Young, “Tunnel Field-Effect Transistors: Prospects and Challenges,” IEEE Journal of the Electron Devices Society 3, no. 3 (2015): 88-95.

[11] D. Esseni, M. Pala, P. Palestri, C. Alper, and T. Rollo, “A Review of Selected Topics in Physics Based Modeling for Tunnel Field-Effect Transistors,” Semiconductor Science and Technology 32, no. 8 (2017): 083005.

[12] G. Nazir, A. Rehman, and S.-J. Park, “Energy-Efficient Tunneling Field-Effect Transistors for Low-Power Device Applications: Challenges and Opportunities,” ACS Applied Materials & Interfaces 12, no. 42 (2020): 47127-47163.

[13] S. Kanungo, G. Ahmad, P. Sahatiya, A. Mukhopadhyay, and S. Chattopadhyay, “2D Materials-Based Nanoscale Tunneling Field Effect Transistors: Current Developments and Future Prospects,” npj 2D Materials and Applications 6, no. 1 (2022): 83.

[14] A. H. Bayani, J. Voves, and D. Dideban, “Effective Mass Approximation Versus Full Atomistic Model to Calculate the Output Characteristics of a Gate-All-Around Germanium Nanowire Field Effect Transistor (GAA-GeNW-FET),” Superlattices and Microstructures 113 (2018): 769-776.

[15] J. L. P. J. van der Steen, D. Esseni, P. Palestri, L. Selmi, and R. J. E. Hueting, “Validity of the Parabolic Effective Mass Approximation in Silicon and Germanium n-MOSFETs With Different Crystal Orientations,” IEEE Transactions on Electron Devices 54, no. 8 (2007): 1843-1851.

[16] Y.-S. Kim, M. Marsman, G. Kresse, F. Tran, and P. Blaha, “Towards Efficient Band Structure and Effective Mass Calculations for III-V Direct Band-Gap Semiconductors,” Physical Review B 82, no. 20 (2010): 205212.

[17] M. Chhowalla, D. Jena, and H. Zhang, “Two-Dimensional Semiconductors for Transistors,” Nature Reviews Materials 1, no. 11 (2016): 16052.

[18] P. Miró, M. Audiffred, and T. Heine, “An Atlas of Two-Dimensional Materials,” Chemical Society Reviews 43, no. 18 (2014): 6537-6554.

[19] M. Rudan, Physics of Semiconductor Devices (Springer, 2015).

[20] A. Beckers, F. Jazaeri, and C. Enz, “Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors,” IEEE Electron Device Letters 41, no. 2 (2020): 276-279.

[21] S. Sahay and M. J. Kumar, “Insight Into Lateral Band-To-Band-Tunneling in Nanowire Junctionless FETs,” IEEE Transactions on Electron Devices 63, no. 10 (2016): 4138-4142.

[22] F. Chen, H. Ilatikhameneh, Y. Tan, G. Klimeck, and R. Rahman, “Switching Mechanism and the Scalability of Vertical-TFETs,” IEEE Transactions on Electron Devices 65, no. 7 (2018): 3065-3068.

[23] W. Cao, D. Sarkar, Y. Khatami, J. Kang, and K. Banerjee, “Subthreshold-Swing Physics of Tunnel Field-Effect Transistors,” AIP Advances 4, no. 6 (2014): 067141.

[24] W. M. Weber and T. Mikolajick, “Silicon and Germanium Nanowire Electronics: Physics of Conventional and Unconventional Transistors,” Reports on Progress in Physics 80, no. 6 (2017): 066502.

[25] M. U. Haque and P. Vimala, “Boosting ON-current in tunnel FETs (TFETs): A Review,” 2022 6th International Conference on Devices, Circuits and Systems (ICDCS) (2022): 294-298.

[26] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation,” IEEE Transactions on Electron Devices 56, no. 9 (2009): 2092-2098.

[27] R. N. Sajjad, W. Chern, J. L. Hoyt, and D. A. Antoniadis, “Trap Assisted Tunneling and Its Effect on Subthreshold Swing of Tunnel FETs,” IEEE Transactions on Electron Devices 63, no. 11 (2016): 4380-4387.

[28] W. G. Vandenberghe, A. S. Verhulst, B. Sorée, et al., “Figure of Merit for and Identification of Sub-60 mV/Decade Devices,” Applied Physics Letters 102, no. 1 (2013): 013510.

[29] M. O. Li, D. Esseni, J. J. Nahas, D. Jena, and H. G. Xing, “Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs),” IEEE Journal of the Electron Devices Society 3, no. 3 (2015): 200-207.

[30] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature,” IEEE Electron Device Letters 32, no. 4 (2011): 437-439.

[31] Y. Shao, M. Pala, H. Tang, et al., “Scaled Vertical-Nanowire Heterojunction Tunnelling Transistors With Extreme Quantum Confinement,” Nature Electronics 8, no. 2 (2025): 157-167.

[32] X. Zhao, A. Vardi, and J. A. del Alamo, “Sub-Thermal Subthreshold Characteristics in Top-Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs,” IEEE Electron Device Letters 38, no. 7 (2017): 855-858.

[33] D. Sarkar, X. Xie, W. Liu, et al., “A Subthermionic Tunnel Field-Effect Transistor With an Atomically Thin Channel,” Nature 526, no. 7571 (2015): 91-95.

[34] J. Miao, C. Leblanc, J. Wang, et al., “Heterojunction Tunnel Triodes Based on Two-Dimensional Metal Selenide and Three-Dimensional Silicon,” Nature Electronics 5, no. 11 (2022): 744-751.

[35] N. T. Duong, C. Park, D. H. Nguyen, et al., “Gate-Controlled MoTe₂ Homojunction for Sub-Thermionic Subthreshold Swing Tunnel Field-Effect Transistor,” Nano Today 40 (2021): 101263.

[36] S. Kim, G. Myeong, W. Shin, et al., “Thickness-Controlled Black Phosphorus Tunnel Field-Effect Transistor for Low-Power Switches,” Nature Nanotechnology 15, no. 3 (2020): 203-206.

[37] N. Oliva, J. Backman, L. Capua, M. Cavalieri, M. Luisier, and A. M. Ionescu, “WSe₂/SnSe₂ vdW Heterojunction Tunnel Fet With Subthermionic Characteristic and MOSFET Co-Integrated on Same WSe₂ Flake,” npj 2D Materials and Applications 4, no. 1 (2020): 5.

[38] L. Liao, Y.-C. Lin, M. Bao, et al., “High-Speed Graphene Transistors With a Self-Aligned Nanowire Gate,” Nature 467, no. 7313 (2010): 305-308.

[39] Y. Liu, J. Guo, E. Zhu, et al., “Approaching the Schottky-Mott Limit in van der Waals Metal-Semiconductor Junctions,” Nature 557, no. 7707 (2018): 696-700.

[40] P. Chen, T. L. Atallah, Z. Lin, et al., “Approaching the Intrinsic Exciton Physics Limit in Two-Dimensional Semiconductor Diodes,” Nature 599, no. 7885 (2021): 404-410.

[41] C. Woo Young Choi, P. Byung-Gook Park, L. Jong Duk Lee, and L. Tsu-Jae King Liu, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Letters 28, no. 8 (2007): 743-745.

[42] Y.-C. Yeo, G. Han, Y. Yang, and P. Guo, “Invited Strain Engineering and Junction Design for Tunnel Field-Effect Transistor,” ECS Transactions 33, no. 6 (2010): 77-87.

[43] K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-Slope Tunnel Field-Effect Transistors Using III-V Nanowire/Si Heterojunction,” 2012 Symposium on VLSI Technology (VLSIT) (2012), 47-48.

[44] L. Lattanzio, L. De Michielis, and A. M. Ionescu, “The Electron-Hole Bilayer Tunnel FET,” Solid-State Electronics 74 (2012): 85-90.

[45] B. Ganjipour, A. W. Dey, B. M. Borg, et al., “High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires,” Nano Letters 11, no. 10 (2011): 4222-4226.

[46] E. Memisevic, J. Svensson, M. Hellenbrand, E. Lind, and L. E. Wernersson, “Vertical InAs/GaAsSb/GaSb Tunneling Field-Effect Transistor on Si With S = 48 mV/decade and I_on = 10 μA/μm for I_off = 1 nA/μm at V_ds = 0.3 V,” 2016 IEEE International Electron Devices Meeting (IEDM) (2016): 19.1.1-19.1.4.

[47] R. M. Iutzi and E. A. Fitzgerald, “Microstructure and Conductance-Slope of InAs/GaSb Tunnel Diodes,” Journal of Applied Physics 115, no. 23 (2014): 234503.

[48] F. Conzatti, M. G. Pala, D. Esseni, E. Bano, and L. Selmi, “Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs,” IEEE Transactions on Electron Devices 59, no. 8 (2012): 2085-2092.

[49] J.-S. Liu, Y. Zhu, P. S. Goley, and M. K. Hudait, “Heterointerface Engineering of Broken-Gap InAs/GaSb Multilayer Structures,” ACS Applied Materials & Interfaces 7, no. 4 (2015): 2512-2517.

[50] E. Memisevic, M. Hellenbrand, E. Lind, et al., “Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating Below 60 mV/Decade,” Nano Letters 17, no. 7 (2017): 4373-4380.

[51] J. Madan and R. Chaujar, “Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability,” IEEE Transactions on Device and Materials Reliability 16, no. 2 (2016): 227-234.

[52] D. Das and C. K. Pandey, “Interfacial Trap Charge and Self-Heating Effect Based Reliability Analysis of a Dual-Drain Vertical Tunnel FET,” Microelectronics Reliability 146 (2023): 115024.

[53] G. Dewey, B. Chu-Kung, J. Boardman, et al., “Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing,” 2011 International Electron Devices Meeting (2011): 33.6.1-33.6.4.

[54] E. Ko, H. Lee, J. D. Park, and C. Shin, “Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers,” IEEE Transactions on Electron Devices 63, no. 12 (2016): 5030-5035.

[55] K. Tomioka, T. Tanaka, S. Hara, K. Hiruma, and T. Fukui, “III-V Nanowires on Si Substrate: Selective-Area Growth and Device Applications,” IEEE Journal of Selected Topics in Quantum Electronics 17, no. 4 (2011): 1112-1129.

[56] A. Kikuchi, R. Bannai, K. Kishino, C.-M. Lee, and J.-I. Chyi, “AlN/GaN Double-Barrier Resonant Tunneling Diodes Grown by RF-Plasma-Assisted Molecular-Beam Epitaxy,” Applied Physics Letters 81, no. 9 (2002): 1729-1731.

[57] K. Ploog, “Delta- (δ-) Doping in MBE-Grown GaAs: Concept and Device Application,” Journal of Crystal Growth 81, no. 1 (1987): 304-313.

[58] A. S. Verhulst, B. Sorée, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, “Modeling the Single-Gate, Double-Gate, and Gate-All-Around Tunnel Field-Effect Transistor,” Journal of Applied Physics 107, no. 2 (2010): 024518.

[59] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤50-mV/decade Subthreshold Swing,” IEEE Electron Device Letters 32, no. 11 (2011): 1504-1506.

[60] N. Kumar, U. Mushtaq, S. I. Amin, and S. Anand, “Design and Performance Analysis of Dual-Gate All Around Core-Shell Nanotube TFET,” Superlattices and Microstructures 125 (2019): 356-364.

[61] Y. Xu, B. Shen, D. Wang, et al. “Study of Synthetic Electric Field Effects and Quantum Confinement Effects in Extremely Scaled Gate-all-Around Tunnel FET,” 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) (2022): 1-3.

[62] A. N. Hanna, H. M. Fahad, and M. M. Hussain, “InAs/Si Hetero-Junction Nanotube Tunnel Transistors,” Scientific Reports 5, no. 1 (2015): 9843.

[63] Y. Yue Yang, T. Xin Tong, Y. Li-Tao yang, G. Peng-Fei guo, F. Lu Fan, and Y. Yee-Chia yeo, “Tunneling Field-Effect Transistor: Capacitance Components and Modeling,” IEEE Electron Device Letters 31, no. 7 (2010): 752-754.

[64] A. Chattopadhyay and A. Mallik, “Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor,” IEEE Transactions on Electron Devices 58, no. 3 (2011): 677-683.

[65] A. Chauhan, G. Saini, and P. K. Yerur, “Improving the Performance of Dual-k Spacer Underlap Double Gate TFET,” Superlattices and Microstructures 124 (2018): 79-91.

[66] C. K. Pandey, D. Dash, and S. Chaudhury, “Approach to Suppress Ambipolar Conduction in Tunnel FET Using Dielectric Pocket,” Micro & Nano Letters 14, no. 1 (2019): 86-90.

[67] H. Ilatikhameneh, T. A. Ameen, G. Klimeck, J. Appenzeller, and R. Rahman, “Dielectric Engineered Tunnel Field-Effect Transistor,” IEEE Electron Device Letters 36, no. 10 (2015): 1097-1100.

[68] A. Saeidi, T. Rosca, E. Memisevic, et al., “Nanowire Tunnel FET With Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current Due to Negative Capacitance and Voltage Pinning Effects,” Nano Letters 20, no. 5 (2020): 3255-3262.

[69] H. Liu, X. Zhou, P. Li, et al., “A Symmetric Heterogate Dopingless Electron-Hole Bilayer TFET With Ferroelectric and Barrier Layers,” Physica Scripta 99, no. 8 (2024): 085007.

[70] A. A. M. Mazumder, K. Hosen, M. S. Islam, and J. Park, “Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaaAs/InN Tunnel FET,” IEEE Access 10 (2022): 30323-30334.

[71] P. Wu and J. Appenzeller, “Design Considerations for 2-D Dirac-Source FETs—Part II: Nonidealities and Benchmarking,” IEEE Transactions on Electron Devices 69, no. 8 (2022): 4681-4685.

[72] W. Gan, K. Luo, G. Qi, et al., “A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET,” IEEE Transactions on Electron Devices 68, no. 11 (2021): 5455-5461.

[73] G. Peng-Fei guo, Y. Li-Tao yang, Y. Yue Yang, et al., “Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current,” IEEE Electron Device Letters 30, no. 9 (2009): 981-983.

[74] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and ≪60 mV/dec Subthreshold Slope, “2008 IEEE International Electron Devices Meeting (2008): 1-3.

[75] A. Villalon, C. L. Royer, M. Cassé, et al. “Strained Tunnel FETs With Record ION: First Demonstration of ETSOI TFETs With SiGe Channel and RSD,” 2012 Symposium on VLSI Technology (VLSIT) (2012): 49-50.

[76] M. Velický and P. S. Toth, “From Two-Dimensional Materials to Their Heterostructures: An Electrochemist's Perspective,” Applied Materials Today 8 (2017): 68-103.

[77] S.-C. Lu, M. Mohamed, and W. Zhu, “Novel Vertical Hetero- and Homo-Junction Tunnel Field-Effect Transistors Based on Multi-Layer 2D Crystals,” 2D Materials 3, no. 1 (2016): 011010.

[78] J. Cao, D. Logoteta, S. Ozkaya, et al., “Operation and Design of van der Waals Tunnel Transistors: A 3-D Quantum Transport Study,” IEEE Transactions on Electron Devices 63, no. 11 (2016): 4388-4394.

[79] H. Ilatikhameneh, G. Klimeck, J. Appenzeller, and R. Rahman, “Design Rules for High Performance Tunnel Transistors From 2-D Materials,” IEEE Journal of the Electron Devices Society 4, no. 5 (2016): 260-265.

[80] T. Agarwal, G. Fiori, B. Soree, I. Radu, M. Heyns, and W. Dehaene, “Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs,” IEEE Journal of the Electron Devices Society 6 (2018): 979-986.

[81] T. K. Agarwal, A. Nourbakhsh, P. Raghavan, et al., “Bilayer Graphene Tunneling FET for sub-0.2 V Digital CMOS Logic Applications,” IEEE Electron Device Letters 35, no. 12 (2014): 1308-1310.

[82] G. Fiori and G. Iannaccone, “Ultralow-Voltage Bilayer Graphene Tunnel FET,” IEEE Electron Device Letters 30, no. 10 (2009): 1096-1098.

[83] H. Ilatikhameneh, Y. Tan, B. Novakovic, G. Klimeck, R. Rahman, and J. Appenzeller, “Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1 (2015): 12-18.

[84] X.-W. Jiang and S.-S. Li, “Performance Limits of Tunnel Transistors Based on Mono-Layer Transition-Metal Dichalcogenides,” Applied Physics Letters 104, no. 19 (2014): 193510.

[85] A. Nourbakhsh, T. K. Agarwal, A. Klekachev, et al., “Chemically Enhanced Double-Gate Bilayer Graphene Field-Effect Transistor With Neutral Channel for Logic Applications,” Nanotechnology 25, no. 34 (2014): 345203.

[86] M. C. Robbins, P. Golani, and S. J. Koester, “Right-Angle Black Phosphorus Tunneling Field Effect Transistor,” IEEE Electron Device Letters 40, no. 12 (2019): 1988-1991.

[87] F. W. Chen, H. Ilatikhameneh, G. Klimeck, Z. Chen, and R. Rahman, “Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET,” IEEE Journal of the Electron Devices Society 4, no. 3 (2016): 124-128.

[88] Y. Wang and M. Chhowalla, “Making Clean Electrical Contacts on 2D Transition Metal Dichalcogenides,” Nature Reviews Physics 4, no. 2 (2022): 101-112.

[89] P. V. Pham, S. C. Bodepudi, K. Shehzad, et al., “2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges,” Chemical Reviews 122, no. 6 (2022): 6514-6613.

[90] I. Popov, G. Seifert, and D. Tománek, “Designing Electrical Contacts to MoS₂ Monolayers: A Computational Study,” Physical Review Letters 108, no. 15 (2012): 156802.

[91] L. Britnell, R. M. Ribeiro, A. Eckmann, et al., “Strong Light-Matter Interactions in Heterostructures of Atomically Thin Films,” Science 340, no. 6138 (2013): 1311-1314.

[92] C. Xi Cao and G. Jing Guo, “Simulation of Phosphorene Field-Effect Transistor at the Scaling Limit,” IEEE Transactions on Electron Devices 62, no. 2 (2015): 659-665.

[93] T. A. Ameen, H. Ilatikhameneh, G. Klimeck, and R. Rahman, “Few-Layer Phosphorene: An Ideal 2D Material for Tunnel Transistors,” Scientific Reports 6, no. 1 (2016): 28515.

[94] J. Seo, S. Jung, and M. Shin, “The Performance of Uniaxially Strained Phosphorene Tunneling Field-Effect Transistors,” IEEE Electron Device Letters 38, no. 8 (2017): 1150-1152.

[95] F. Liu, Q. Shi, J. Wang, and H. Guo, “Device Performance Simulations of Multilayer Black Phosphorus Tunneling Transistors,” Applied Physics Letters 107, no. 20 (2015): 203501.

[96] P. Wu, T. Ameen, H. Zhang, et al., “Complementary Black Phosphorus Tunneling Field-Effect Transistors,” ACS Nano 13, no. 1 (2019): 377-385.

[97] P. Wu and J. Appenzeller, “Reconfigurable Black Phosphorus Vertical Tunneling Field-Effect Transistor With Record High On-Currents,” IEEE Electron Device Letters 40, no. 6 (2019): 981-984.

[98] C. Gong, H. Zhang, W. Wang, L. Colombo, R. M. Wallace, and K. Cho, “Band Alignment of Two-Dimensional Transition Metal Dichalcogenides: Application in Tunnel Field Effect Transistors,” Applied Physics Letters 103, no. 5 (2013): 053513.

[99] V. O. Özçelik, J. G. Azadani, C. Yang, S. J. Koester, and T. Low, “Band Alignment of Two-Dimensional Semiconductors for Designing Heterostructures With Momentum Space Matching,” Physical Review B 94, no. 3 (2016): 035125.

[100] Y. Cai, G. Zhang, and Y.-W. Zhang, “Layer-Dependent Band Alignment and Work Function of Few-Layer Phosphorene,” Scientific Reports 4, no. 1 (2014): 6677.

[101] K. Cheng, Y. Guo, N. Han, Y. Su, J. Zhang, and J. Zhao, “Lateral Heterostructures of Monolayer Group-IV Monochalcogenides: Band Alignment and Electronic Properties,” Journal of Materials Chemistry C 5, no. 15 (2017): 3788-3795.

[102] Z. Guo, J. Zhou, L. Zhu, and Z. Sun, “MXene: A Promising Photocatalyst for Water Splitting,” Journal of Materials Chemistry A 4, no. 29 (2016): 11446-11452.

[103] Y. Liang, Y. Dai, Y. Ma, L. Ju, W. Wei, and B. Huang, “Novel Titanium Nitride Halide TiNX (X = F, Cl, Br) Monolayers: Potential Materials for Highly Efficient Excitonic Solar Cells,” Journal of Materials Chemistry A 6, no. 5 (2018): 2073-2080.

[104] W. Li, F. P. Sabino, F. Crasto de Lima, T. Wang, R. H. Miwa, and A. Janotti, “Large Disparity Between Optical and Fundamental Band Gaps in Layered In₂Se₃,” Physical Review B 98, no. 16 (2018): 165134.

[105] A. Szabo, C. Klinkert, D. Campi, C. Stieger, N. Marzari, and M. Luisier, “Ab Initio Simulation of Band-to-Band Tunneling FETs With Single- and Few-Layer 2-D Materials as Channels,” IEEE Transactions on Electron Devices 65, no. 10 (2018): 4180-4187.

[106] Z. Wu, Y. Lyu, Y. Zhang, et al., “Large-Scale Growth of Few-Layer Two-Dimensional Black Phosphorus,” Nature Materials 20, no. 9 (2021): 1203-1209.

[107] Y. Zhao, J. Mao, Z. Wu, et al., “A Clean Transfer Approach to Prepare Centimetre-Scale Black Phosphorus Crystalline Multilayers on Silicon Substrates for Field-Effect Transistors,” Nature Communications 15, no. 1 (2024): 6795.

[108] S. Kamaei, A. Saeidi, C. Gastaldi, et al., “Gate Energy Efficiency and Negative Capacitance in Ferroelectric 2D/2D TFET From Cryogenic to High Temperatures,” npj 2D Materials and Applications 5, no. 1 (2021): 76.

[109] C. Qiu, F. Liu, L. Xu, et al., “Dirac-Source Field-Effect Transistors as Energy-Efficient, High-Performance Electronic Switches,” Science 361, no. 6400 (2018): 387-392.

[110] X. Yan, C. Liu, C. Li, et al., “Tunable SnSe₂/WSe₂ Heterostructure Tunneling Field Effect Transistor,” Small 13, no. 34 (2017): 1701478.

[111] Y. Sato, T. Nishimura, D. Duanfei, et al., “Intrinsic Electronic Transport Properties and Carrier Densities in PtS₂ and SnSe₂: Exploration of n⁺-Source for 2D Tunnel FETs,” Advanced Electronic Materials 7, no. 12 (2021): 2100292.

[112] J. He, N. Fang, K. Nakamura, et al., “2D Tunnel Field Effect Transistors (FETs) With a Stable Charge-Transfer-Type P⁺-WSe₂ Source,” Advanced Electronic Materials 4, no. 7 (2018): 1800207.

[113] X. Jiang, X. Shi, M. Zhang, et al., “A Symmetric Tunnel Field-Effect Transistor Based on MoS₂/Black Phosphorus/MoS₂ Nanolayered Heterostructures,” ACS Applied Nano Materials 2, no. 9 (2019): 5674-5680.

[114] H. Zhang, W. Cao, J. Kang, and K. Banerjee, “Effect of Band-tails on the Subthreshold Performance of 2D Tunnel-FETs.” 2016 IEEE International Electron Devices Meeting (IEDM) (2016): 30.3.1-30.3.4.

[115] Q. Zhang, Y. Xiong, Y. Gao, J. Chen, W. Hu, and J. Yang, “First-Principles High-Throughput Inverse Design of Direct Momentum-Matching Band Alignment van der Waals Heterostructures Utilizing Two-Dimensional Indirect Semiconductors,” Nano Letters 24, no. 12 (2024): 3710-3718.

[116] Y.-J. Zhang, Y.-T. Ren, X.-H. Lv, et al., “Momentum Matching and Band-Alignment Type in van der Waals Heterostructures: Interfacial Effects and Materials Screening,” Physical Review B 107, no. 23 (2023): 235420.

[117] W. Zhou, H. Qu, S. Guo, et al., “Dependence of Tunneling Mechanism on Two-Dimensional Material Parameters: A High-Throughput Study,” Physical Review Applied 17, no. 6 (2022): 064053.

[118] C. Huang, S. Wu, A. M. Sanchez, et al., “Lateral Heterojunctions Within Monolayer MoSe₂-WSe₂ Semiconductors,” Nature Materials 13, no. 12 (2014): 1096-1101.

[119] X. Duan, C. Wang, J. C. Shaw, et al., “Lateral Epitaxial Growth of Two-Dimensional Layered Semiconductor Heterojunctions,” Nature Nanotechnology 9, no. 12 (2014): 1024-1030.

[120] H. Bergeron, D. Lebedev, and M. C. Hersam, “Polymorphism in Post-Dichalcogenide Two-Dimensional Materials,” Chemical Reviews 121, no. 4 (2021): 2713-2775.

[121] J. Yu, C.-Y. Xu, F.-X. Ma, S.-P. Hu, Y.-W. Zhang, and L. Zhen, “Monodisperse SnS₂ Nanosheets for High-Performance Photocatalytic Hydrogen Generation,” ACS Applied Materials & Interfaces 6, no. 24 (2014): 22370-22377.

[122] P. G. D. Agopian, J. A. Martino, A. Vandooren, et al., “Study of Line-TFET Analog Performance Comparing With Other TFET and MOSFET Architectures,” Solid-State Electronics 128 (2017): 43-47.

[123] J. Yu, W. Han, A. A. Suleiman, S. Han, N. Miao, and F. C.-C. Ling, “Recent Advances on Pulsed Laser Deposition of Large-Scale Thin Films,” Small Methods 8, no. 7 (2024): 2301282.

[124] P. M. Campbell, J. K. Smith, W. J. Ready, and E. M. Vogel, “Material Constraints and Scaling of 2-D Vertical Heterostructure Interlayer Tunnel Field-Effect Transistors,” IEEE Transactions on Electron Devices 64, no. 6 (2017): 2714-2720.

[125] J. Cao, D. Logoteta, M. G. Pala, and A. Cresti, “Impact of Momentum Mismatch on 2D van der Waals Tunnel Field-Effect Transistors,” Journal of Physics D: Applied Physics 51, no. 5 (2018): 055102.

[126] H. Li, P. Xu, L. Xu, Z. Zhang, and J. Lu, “Negative Capacitance Tunneling Field Effect Transistors Based on Monolayer Arsenene, Antimonene, and Bismuthene,” Semiconductor Science and Technology 34, no. 8 (2019): 085006.

[127] W. Gonçalez Filho, E. Simoen, R. Rooyackers, et al., “Analog Design With Line-TFET Device Experimental Data: From Device to Circuit Level,” Semiconductor Science and Technology 35, no. 5 (2020): 055025.

[128] Z. Yang, Z. Wu, Y. Lyu, and J. Hao, “Centimeter-Scale Growth of Two-Dimensional Layered High-Mobility Bismuth Films by Pulsed Laser Deposition,” InfoMat 1, no. 1 (2019): 98-107.

[129] B. Rawat and R. Paily, “Analysis of Graphene Tunnel Field-Effect Transistors for Analog/RF Applications,” IEEE Transactions on Electron Devices 62, no. 8 (2015): 2663-2669.

[130] G. Alymov, V. Vyurkov, V. Ryzhii, and D. Svintsov, “Abrupt Current Switching in Graphene Bilayer Tunnel Transistors Enabled by van Hove Singularities,” Scientific Reports 6, no. 1 (2016): 24654.

[131] Q. Zhang, G. Iannaccone, and G. Fiori, “Two-Dimensional Tunnel Transistors Based on Bi₂Se₃ Thin Film,” IEEE Electron Device Letters 35, no. 1 (2014): 129-131.

[132] G. V. Resta, A. Leonhardt, Y. Balaji, S. De Gendt, P. E. Gaillardon, and G. De Micheli, “Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 7 (2019): 1486-1503.

[133] J. Chang, L. F. Register, and S. K. Banerjee, “Possible Applications of Topological Insulator Thin Films for Tunnel FETs,” in 70th Device Research Conference (IEEE, 2012), 31-32.

[134] Y. Bi, K. Shamsi, J. S. Yuan, Y. Jin, M. Niemier, and X. S. Hu, “Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs,” IEEE Transactions on Emerging Topics in Computing 5, no. 3 (F2017): 340-352.

[135] A. Nourbakhsh, A. Zubair, M. S. Dresselhaus, and T. Palacios, “Transport Properties of a MoS₂/WSe₂ Heterojunction Transistor and Its Potential for Application,” Nano Letters 16, no. 2 (2016): 1359-1366.

[136] J. Shim, S. Oh, D.-H. Kang, et al., “Phosphorene/Rhenium Disulfide Heterojunction-Based Negative Differential Resistance Device for Multi-Valued Logic,” Nature Communications 7, no. 1 (2016): 13413.

RIGHTS & PERMISSIONS

2025 The Author(s). Interdisciplinary Materials published by Wuhan University of Technology and John Wiley & Sons Australia, Ltd.