System-level Pareto frontiers for on-chip thermoelectric coolers

Abstract

The continuous rise in heat dissipation of integrated circuits necessitates advanced thermal solutions to ensure system reliability and efficiency. Thermoelectric coolers are among the most promising techniques for dealing with localized on-chip hot spots. This study focuses on establishing a holistic optimization methodology for such thermoelectric coolers, in which a thermoelectric element’s thickness and the electrical current are optimized to minimize source temperature with respect to ambient, when the thermal and electrical parasitic effects are considered. It is found that when element thickness and electrical current are optimized for a given system architecture, a “heat flux vs. temperature difference” Pareto frontier curve is obtained, indicating that there is an optimum thickness and a corresponding optimum current that maximize the achievable temperature reduction while removing a particular heat flux. This methodology also provides the possible system level ΔT’s that can be achieved for a range of heat fluxes, defining the upper limits of thermoelectric cooling for that architecture. In this study, use was made of an extensive analytical model, which was verified using commercially available finite element analysis software. Through the optimization process, 3 pairs of master curves were generated, which were then used to compose the Pareto frontier for any given system architecture. Finally, a case study was performed to provide an in-depth demonstration of the optimization procedure for an example application.

Keywords

thermoelectric cooling / thermal management / optimization / high flux electronics

Introduction

Thermoelectric (TE) devices are solid state heat pumps that can be used for various purposes such as refrigeration and temperature stabilization. Their use in electronic cooling applications are extensively studied and explored [¹–³]. Although their coefficients of performance (COPs) are considerably lower than other refrigeration cycles, the fact that they can be scaled to such small sizes and have no moving parts make them advantageous in electronic cooling applications. This is particularly so for high flux electronics and military applications where lower COPs can be tolerated, because the prime purpose is to minimize the chip temperatures to ensure high reliability and chip efficiency. There are a number of studies focused on embedded thermoelectric cooling using thin film devices, demonstrating that thinner TECs are capable of removing very high localized heat fluxes and remediate chip hotspots [⁴–¹¹].

The fundamental thermoelectric equations governing the heat pumped by a TE element are shown below [¹–³]. An electric current I passes through an element of length L and cross-sectional area Awhich results in rate of heat absorbed Q_c at the cold junction of the element and heat released Q_h at the hot junction of the element.

(1){{\displaystyle Q}}_{\mathrm{c}}={{\displaystyle ST}}_{\mathrm{c}}I-{\displaystyle \frac{\mathrm{1}}{\mathrm{2}}}{I}^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec,TE}}-K\left({{\displaystyle T}}_{\mathrm{h}}-{{\displaystyle T}}_{\mathrm{c}}\right),

(2){{\displaystyle Q}}_{\mathrm{h}}={{\displaystyle ST}}_{\mathrm{h}}I-{\displaystyle \frac{\mathrm{1}}{\mathrm{2}}}{I}^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec,TE}}-K\left({{\displaystyle T}}_{\mathrm{h}}-{{\displaystyle T}}_{\mathrm{c}}\right),

(3){{\displaystyle R}}_{\mathrm{elec,TE}}=\rho {\displaystyle \frac{L}{{{\displaystyle A}}_{\mathrm{T}\mathrm{E}}}},

(4)K=k{\displaystyle \frac{{{\displaystyle A}}_{\mathrm{T}\mathrm{E}}}{L}},

where S is the seebeck coefficient of the element, r is electrical resistivity, and k is thermal conductivity, K is the thermal conductance and R_elec,TE is the electrical resistance of the TE element. T_c and T_h are the steady-state temperature of the cold and hot junction, respectively, and Q_h is the heat rejected at the hot junction–larger than Q_c by an amount I²R_TE+ SI(T_h–T_c). There are various electrical and thermal resistances discussed throughout the paper, thus to better communicate with the readers, the electrical resistances are denoted with “elec” subscript. Any resistance that is not denoted with “elec” subscript signifies that it is a thermal resistance.

It is a well-established fact that a thermoelectric cooler’s maximum heat pumping capacity can be significantly increased by decreasing the thickness of the semiconductor legs that form the TE elements [¹–³,⁷–¹⁵]. Shorter legs decrease the electrical resistance of the semiconductor, which in turn allows operation at larger electrical currents and thus enables larger cooling power. It can be derived from the thermoelectric equations above that the maximum cooling power Q_c, achieved when the temperature difference between the cold and hot junctions is zero ΔT_e = (T_h– T_c) = 0, is inversely proportional to the element thickness. A very recent study has experimentally reached 258 W/cm² heat flux with an 8 µm thick Bi₂Te₃ based TE element where they measured their device levelΔT = 0 [⁷].

However, a real thermoelectric module consists of not only thermoelectric elements, but also headers, metal trace layers and adhesion layers. And, as shown in Fig. 1, a thermoelectric module is usually attached to a heat sink in practical cooling applications. Therefore, these parasitic thermal and electrical resistances need to be considered in the design and analysis of thermoelectric cooling systems. It is important to note that a decrease in the leg thickness also leads to a decrease in the maximum achievable system-level ΔT_sys at zero external heat flux. This is because as the TE thickness “L” is decreased, the thermal conductance of the TE element “K” increases, leading to a larger thermal back conduction from the hot junction to the cold junction and lowering the achievable ΔT_e. From an application point of view, thermoelectric coolers are typically designed to generate a desired amount of system-level ΔT_sys = (T_sink– T_sourcs) at a given cooling heat flux. Thinning down the material to further increase the cooling flux at the expense of decreasing available ΔT_sys may not be the best strategy in all cases. This phenomenon has been discovered and discussed in other studies [¹⁴,¹⁵], where the thickness is optimized for better thermoelectric cooling.

The optimum thickness and electrical current depend highly on the architectural structure of the system, where the mentioned thermal and electrical parasitics impact the seoptimal values. The external thermal parasitics result in a lower system-level temperature difference, ΔT_sys, established between the active heat dissipating surface to be cooled (source) and the ambient to which heat is rejected (sink) than the ΔT_e established across the TE elements. Meanwhile, the external electrical parasitics result in a discrepancy between the heat dissipated by the source, Q_s, and the heat that must be absorbed by the cold junction Q_c.

Thus, this optimization study focuses on two novel interrelated topics, that are of utmost importance for accurate analysis and design of thermal management schemes involving thermoelectric coolers. First, optimizing both thickness and current to minimize the source temperature (w.r.t. constant ambient temperature) traces out a Pareto frontier curve for Q_s vs ΔT_sys, which indicates the limitations of thermoelectric cooling for a given system architecture. Second, particular attention is paid to the effects of the system-level thermal/electrical parasitics on the optimized thickness and electrical current, which in turn dictates the shape and bounds of the associated Pareto frontier. An analytical system-level model is formulated and verified using commercially available finite element modeling (FEM) software, Ansys-Workbench. Finally, a case study is performed to provide an in-depth demonstration of the optimization procedure for an example application. The material properties of the thermoelectric element are chosen as S =±220 µV/K (opposite in sign, same in magnitude for p- and n-type legs), k = 1.25 /W(m·K), and r = 1 × 10⁻⁵W·m, that comes to a ZT value of 1.2 at 300 K, which are typical values for Bi₂Te₃ type thermoelectric materials [¹⁶].

Pareto frontier curve and optimization methodology

To understand how the Pareto frontier curve is formed, Fig. 2(a) demonstrates device-level cooling curves of 3 different TE element thicknesses, where the unit cell based device (see Fig. 7) is assumed to have structural parasitic thermal resistance, R_str summing up to 20 K/W per unit cell. The curves are generated using the revised TE equations (Eqs. (9)–(12)), which will be discussed in detail. For the shown curves, one can easily see that if the heat flux is higher than 100 W/cm², the device with 10 µm elements would result in larger ΔT_sys than the device with 50 µm element thickness. However, for applications where the heat flux value is less than 100 W/cm², 50 µm elements perform better. The same situation exists between the 50 and 500 µm curves, but at a threshold value where the two curves intersect at ~5 W/cm². This illustrates that there exists an optimum thickness for any given heat flux value that can be obtained by considering more and more choices of thickness. By plotting the envelope of these separate cooling curves, the Pareto frontier curve shown in Fig. 2(b) is obtained. The individual pumping curves for a device of fixed element thickness are tangent to this frontier. Of course, the bounds and shape of the frontier depends on many parameters such as the operating temperature, system level structural resistances, and packing fraction of the device. Besides demonstrating the optimum thickness dependency on heat flux, it is also useful to understand the limits of a thermoelectric cooler in terms of the achievable system-level ΔT_sys at a specific heat flux.

As discussed before, the system-level (structural) thermal resistances have an impact on cooler performance. These include thermal contact resistances, solder layers, ceramic headers, and especially convective resistance between the cooler and ambient sink. The sum of these resistances is defined as

(5){{\displaystyle R}}_{\mathrm{str}}={{\displaystyle R}}_{\mathrm{layer},\mathrm{1}}+{{\displaystyle R}}_{\mathrm{layer},\mathrm{2}+...+}{{\displaystyle R}}_{\mathrm{layer},n}+{{\displaystyle R}}_{\mathrm{thermal}\hspace{0.17em}\mathrm{contact}\hspace{0.17em}\mathrm{resis}\tan \mathrm{ces}}+{{\displaystyle R}}_{\mathrm{convection}}.

Because some structural resistances carry flux Q_s and others carry Q_h which is larger in magnitude, it is useful to categorize them based on location within the thermal path:

(6){{\displaystyle R}}_{\mathrm{str}}={{\displaystyle R}}_{\mathrm{source}}+{{\displaystyle R}}_{\mathrm{sink}},

where R_source includes all of the layers between the heat source and TE element cold junction, and R_sink includes all of the layers after the TE hot junction, with an additional convective resistance term.

The structural thermal resistance has a strong influence on the frontier curve and the corresponding optimal variables. For this reason, the thermoelectric equation alone is unfortunately not enough to analyze a system where the structural thermal resistance are comparable to that of the TE element. This can be explained by realizing that in the presence of structural resistance, the temperature difference across the semiconductor legs does not reflect the actual temperature difference across the module (or system), as seen in Fig. 3. This necessitates integrating the thermal and electrical parasitics into the thermoelectric cooling equation for accurate system-level analysis.

The electrical contact resistances, r_ECR, and the Cu trace resistances, R_elec,trace, are added to Eq. (1) by replacing the term R_elec,TE with R_elec,eff, which is defined as

(7){{\displaystyle R}}_{\mathrm{elec},\mathrm{eff}}={{\displaystyle R}}_{\mathrm{elec},\mathrm{T}\mathrm{E}}+\mathrm{2}\left({\displaystyle \frac{{\rho }_{\mathrm{E}\mathrm{C}\mathrm{R}}}{{{\displaystyle A}}_{\mathrm{T}\mathrm{E}}}}+{{\displaystyle R}}_{\mathrm{elec},\mathrm{trace}}\right).

Thus the revised thermoelectric equations become:

(8){{\displaystyle Q}}_{\mathrm{c},\mathrm{rev}}={{\displaystyle Q}}_{\mathrm{s}}={{\displaystyle ST}}_{\mathrm{c}}I-{\displaystyle \frac{\mathrm{1}}{\mathrm{2}}}{I}^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec},\mathrm{eff}}-K\left({{\displaystyle T}}_{\mathrm{h}}-{{\displaystyle T}}_{\mathrm{c}}\right),

(9){{\displaystyle Q}}_{\mathrm{h},\mathrm{rev}}={{\displaystyle ST}}_{\mathrm{h}}I+{\displaystyle \frac{\mathrm{1}}{\mathrm{2}}}{I}^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec},\mathrm{eff}}-K\left({{\displaystyle T}}_{\mathrm{h}}-{{\displaystyle T}}_{\mathrm{c}}\right),

where the discrepancy between Q_h,rev and Q_s is by the amount I²[R_elec,eff−R_elec,TE]/2.

For the thermal parasitics, the hot and cold junction temperatures T_c and T_h can be written in the forms below,

(10)\Delta {{\displaystyle T}}_{\mathrm{source}}={{\displaystyle T}}_{\mathrm{source}}-{{\displaystyle T}}_{\mathrm{c}}={{\displaystyle Q}}_{\mathrm{s}}{{\displaystyle R}}_{\mathrm{source}},

(11)\Delta {{\displaystyle T}}_{\mathrm{sink}}={{\displaystyle T}}_{\mathrm{h}}-{{\displaystyle T}}_{\mathrm{sink}}={{\displaystyle Q}}_{\mathrm{h},\mathrm{r}\mathrm{e}\mathrm{v}}{{\displaystyle R}}_{\mathrm{sink}},

where T_sink could either be the temperature of the fluid (if the convective resistance is taken into consideration in R_sink) or it can be taken as the surface temperature of the last solid layer if a fixed temperature boundary is assumed. Solving Eqs. (8)–(11) simultaneously and performing some algebraic manipulation, the equation defining the source side temperature is given as:

{{\displaystyle T}}_{\mathrm{source}}={{\displaystyle R}}_{\mathrm{source}}{{\displaystyle Q}}_{\mathrm{s}}+

(12){\displaystyle \frac{{{\displaystyle Q}}_s+{\displaystyle \frac{\mathrm{1}}{\mathrm{2}}}{I}^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec},\mathrm{eff}}+\varphi \left[{{\displaystyle T}}_{\sin \mathrm{k}}+{{\displaystyle R}}_{\sin \mathrm{k}}\left({{\displaystyle Q}}_{\mathrm{s}}+I^{\mathrm{2}}{{\displaystyle R}}_{\mathrm{elec},\mathrm{eff}}\right)\right]}{SI+\varphi }},

where \varphi for convenience is defined as

(13)\varphi ={\displaystyle \frac{K}{\mathrm{1}-{{\displaystyle R}}_{\sin \mathrm{k}}SI}}.

It is this equation that is then optimized to achieve the lowest possible T_source for a given T_sink and Q_s. The optimization variables considered are the current I and the element thickness L, which influences R_elec,eff and K. It is important to keep in mind that Eq. (12) is defined per TE leg, where the unit for Q_s is in Watts and units for R_source and R_sink are in K/W.

Effect of electrical parasitics

The previous section introduced the importance of both thermal and electrical parasitics in the system and their effects on thermoelectric cooling behavior. In this section, the effect of electrical parasitics is discussed in more detail. In thermoelectric cooling, joule heating is the main factor that restricts the optimum current because it has a quadratic relationship with current while the Seebeck cooling term has a linear relationship. Therefore after a certain value, increasing the electrical current does not further improve the performance, and that value is the optimum current for that device. Therefore, decreasing the electrical resistance in the current path allows operating with higher current and thus improves the maximum cooling flux capacity.

In the revised form of the thermoelectric Eq. (8), we have already introduced an effective electrical resistance that includes the ECR (Electrical contact resistances) and the electrical resistances due to the Cu traces within the module. These two parasitics are of minor importance for bulk TECs, where the total electrical resistance is dominated by the thick thermoelectric elements. However, when approaching the thin film regime, the parasitics constitute a much larger portion of the total electrical resistance as can be seen in Fig. 4, which makes it an important concern for high flux thin-film thermoelectric cooling applications.

The significance of electrical contact resistances are well known in the thermoelectric cooling community and there are studies for measuring and decreasing them for better device performances [¹⁷]. From a thermal design standpoint, it is important to know how the ECR limits the performance and what could be achieved if the resistances could be minimized. Figure 5 demonstrates the achievable cooling fluxes at ΔT_sys = 0 for various system level structural resistances. Results clearly indicate that as both thermal and electrical parasitic resistances are eliminated, heat fluxes over 1 kW/cm² are achievable.

The second added term contributing to the overall electrical resistance is the resistance of the Cu traces carrying the current from one TE element to another. Unlike ECR, the traces have both thermal and electrical resistances that simultaneously affect the system performance, and it is possible to perform an optimization on their thickness to enhance cooler performance.

For bulk TECs, where the electrical resistance of the module is already dominated by the thick TE leg, the electrical current is not very high and thus an optimization of the Cu trace thickness yields limited benefit. However, when approaching the thin film regime, the operating electrical current is significantly increased and can cause tremendous amount of joule heating. Over-increasing the trace thickness to circumvent joule heating will start to limit the performance due to the increased thermal resistance in the heat flow pathway. Therefore, there is a certain optimum Cu trace thickness, unique for each of the sink and source sides, that minimizes the degradation on the device performance. It is important to note that while both sides experience the same electrical current flow, the sink side experiences much higher heat fluxes than the source side. Therefore, the optimized thickness of the source side Cu trace is always larger than the sink side Cu trace.

To demonstrate this effect, an aggressively reduced value for electrical contact resistance is chosen (10⁻¹²W·m²) whereby the trace resistance is the dominant parasitic. The optimum thickness of the sink-side Cu trace is found which maximizes the cooling flux Q_max at ΔT_sys = 0. The geometry of the source and sink side in the optimization study are those used in the FEM validation (discussed in the next section). The convective boundary condition was specified as HTC= 200000 W/(m²·K) at T_sink = 400 K, reflective of power electronics cooled by a microchannel cold plate [¹⁸–²²]. In a more comprehensive optimization study, the change in the Cu trace thickness would also change the optimum TE element thickness, but for simplicity the element thickness is fixed at 20 µm. Also shown in Fig. 6 is the resulting Q_max when incorporating only trace conductive thermal resistance and only trace joule heating. These are obtained by setting trace thermal resistivity and electrical resistivity in turn to zero. Expectedly, the optimum thickness is located where the two parasitic curves intersect. For this particular case, the optimum thickness was found to be 40 µm.

In the following sections of this study, the electrical contact resistance and Cu trace thicknesses on both sink and source side have fixed values at 1 × 10⁻¹⁰W·m² and 50 µm respectively, which are within the range of today’s capabilities [¹²,¹⁷]. They are kept constant throughout the optimization and case study sections of the paper.

Analytical model verification

As can be seen in Eq. (12), the source side temperature depends on various parameters including material properties K, R_elec,eff, S and other parameters such as Q_s, T_sink, R_source, R_sink, L, I of which I and L can be simultaneously optimized to minimize T_source for a given architecture. To verify the viability of the equation before starting the optimization process, a numerical model was built on commercially available FEM software ANSYS-Workbench, and T_source was obtained for various model parameters. The model used in this study is a single unit cell, assuming a fixed 50% element area packing fraction with a TE element footprint of 250 µm × 250 µm and header footprint of 350 µm × 350 µm, as shown in Fig. 7.

For the analytical model, the thermal resistance of each solid layer and for the convection boundary is calculated. Because there is change in area from the TE element to the Cu layer and the ceramic header, the constriction and spreading resistances for affected layers are calculated using analytical correlations from Lee et al. [²³]. The resultant sink and source side resistances are found to be R_sink = 427 K/W and R_source = 18 K/W per TE leg (the unit cell). The large disparity between the two thermal resistances is due to the impact of the fluid convection boundary.

All of the structural parameters along with the boundary conditions were substituted into Eq. (12) to analytically calculate the source side temperature. Results and comparison for a wide variety of boundary conditions are shown in Fig. 8, where TE thickness L, electrical current I, T_sink and heat flux values are varied. The dots represent the numerical findings for the given conditions and the lines represent the analytical results, which are found to have very good agreement with each other.

Moreover, calculations were performed with the analytical model to compare the results from an experimental study conducted by Bulman et al. [⁷]. The dimensions (TE element thickness (8.1 µm) and dimensions of other layers) and material properties were taken from that study. The heat load curve was generated using the analytical model and the results have a good agreement with the reported experimental findings as shown in Fig. 9.

Optimization results and discussion

In order for the thermoelectric cooler to achieve higher cooling fluxes, the external structural resistances must be minimized. As discussed before, the convective resistance generally dominates the overall structural resistance, making it the bottleneck of the system on the sink side. On the source side, the resistances can be high enough to be comparable to that of the sink side if the thermoelectric cooling is enhanced by a mini-contact pillar, which concentrates the cooling flux of the TEC on a much smaller heat source, such as a hotspot [⁴–⁶]. However, in many electronic cooling applications this is not the case and the source side resistance will be a much smaller portion of the overall structural resistance.

For applications where thermoelectric coolers are utilized, it is important to understand the limitations of a design. The frontier line which was introduced in the previous sections is a good way to predict the performance of a design at the system level. Thus, a wide analytical optimization study is carried out to give a general overlook on the system-level behavior of thermoelectric cooling, where the sink- and source-side resistances are incorporated into the analysis. Using Eq. (12), it is possible to do a multi-variable, single-objective optimization where both thermoelectric element thickness and TEC electrical current are optimized to obtain the minimum source temperature. Because system ΔT_sys and Q_s are linked one-to-one along the Pareto frontier, together they form the single objective to be maximized. Thus, the optimization can be achieved by either holding Q_s constant and maximizing ΔT_sys (as in Eq. (12)) or vice versa. The first pair of graphs in Fig. 9 represents maximized cooling fluxes while holding the system ΔT_sys (from source to sink) constant, with the left graph representing the results at T_sink = 300 K and right at T_sink = 400 K. The other two pairs of graphs in Fig. 10 and Fig. 11 are the corresponding optimized thickness and current densities, respectively. The resistances R_str and electrical currents are converted to area-based resistance R_str,areal and current density in order to be used as an approximate guide for other geometries as well. Two temperatures, 300 K and 400 K are considered as the fluid temperature to mimic air cooling and two-phase cooling on the sink side for power electronic cold plates. Considering that the percentage of sink and source side resistances contributing to the overall structural resistance has significant effect on the optimal geometries and performance, a new variable gamma is introduced as,

(14)\gamma ={\displaystyle \frac{{{\displaystyle R}}_{\sin \mathrm{k}}}{{{\displaystyle R}}_{\mathrm{str}}}}.

The influence of this ratio on the optimal geometry and cooling is reduced as the R_str approaches zero, as demonstrated in Figs. 10–12. All of the temperature differences in the graphs are system level ΔT_sys.

Applications in which thermoelectric cooling is used vary in the method of heat rejection from the hot junction to the environment. Typically for traditional or bulk TECs the heat removal is handled by an air cooled system where the heat transfer coefficient (HTC) is very limited [¹⁶]. Superior cooling mechanisms such as liquid cooling or two phase cooling are required in order to operate with thinner TECs and higher heat fluxes. Figure 10 shows various system level ΔT_sys curves and their achievable heat fluxes as a function of R_str,areal. As a guide, the graphs in Figs. 10–12 are divided into four regions, demonstrating the heat flux capabilities per different sink side cooling mechanisms based on their achievable HTCs. The heat transfer coefficients are converted to areal resistances simply by R_conv,areal = 1/h and later on converted from m² to cm². The maximum HTCs used in formation of the bands are 200 kW/(m²·K) for two-phase cooling, 20 kW/(m²·K), for liquid cooling and 500 W/(m²·K) for air cooling [¹⁸–²²,²⁴]. It can be seen from the figures that while air cooling can allow heat pumping up to 3–5 W/cm², liquid cooling can allow the TEC to pump up to 50–100 W/cm². Two-phase cooling, on the other hand, enables up to 300–400 W/cm². The white region on the left contains systems that exist in the theoretical limit of zero structural thermal resistance. Even with a perfect convection boundary condition, i.e. fixed temperature, the structural resistances due to ceramic headers, Cu traces and solder layers limit the performance.

The region below 1×10⁻² cm²K/W is especially unrealistic, as such R_str,areal would require that even the Cu traces should be eliminated, which implies almost element-level thermoelectric cooling. However, it is important to note that the results shown in Figs. 10–12 still include the electrical parasitics, meaning that Eq. (12) does not converge (in the limit) to Eq. (1) without also allowing Eq. (7) to converge to the element-only electrical resistance.

Case study

The master curves generated in the previous section are the links that connect the system-level architecture with the frontier curves. For a given R_str, a line crossing each one of the ΔT curves would give the corresponding achievable heat flux value. Thus, if plotted, a Pareto frontier for that particular structural resistance is obtained. To demonstrate this, a power electronic case study is performed. A thermoelectric cooler to be designed for an embedded cooling system architecture is investigated. The sink side will be subjected to evaporative cooling that can provide an effective base HTC of 50000 W/(m²·K). The TEC has 1.4 mm × 1.4 mm footprint, 16 TE elements at 50% packing fraction, and it is bonded to a silicon chip substrate and an aluminum microchannel heat sink with 10 µm thick Sn solder. For simplicity, the fluid saturation temperature is assumed to be 400 K (127°C) and the heat flux from the Si chip is 50 W/cm². In such a scenario, we are demonstrating the optimization procedure to find the optimal TE element gemoetry and the optimum electrical current to minimize the source chip temperature.

Since the architecture of the system is known from Table 1 and Fig. 13, the structural resistances can be calculated as,

(15){{\displaystyle R}}_{\mathrm{str}}={\displaystyle \frac{{{\displaystyle L}}_{\mathrm{1}}}{{{\displaystyle k}}_{\mathrm{1}}{{\displaystyle A}}_{\mathrm{1}}}}+{\displaystyle \frac{{{\displaystyle L}}_{\mathrm{2}}}{{{\displaystyle k}}_{\mathrm{2}}{{\displaystyle A}}_{\mathrm{2}}}}+\cdots +{{\displaystyle R}}_{\mathrm{spr},\mathrm{1}}+{{\displaystyle R}}_{\mathrm{spr},\mathrm{2}}+\cdots +{\displaystyle \frac{\mathrm{1}}{hA}}.

Based on the given geometry and convective boundary condition, we find R_sink = 12.76 K/W and R_source = 1.48 K/W, summing to R_structural = 14.25 K/W with \gamma =\mathrm{0.9}.

One way of determining the optimum thermoelectric element geometry and current is graphically by using the curves provided in the Figs. 10–12. To do that, the areal structural resistances should be obtained first by:

(16){{\displaystyle R}}_{\mathrm{str},\mathrm{areal}}={{\displaystyle R}}_{\mathrm{str}}\times {{\displaystyle A}}_{\mathrm{T}\mathrm{E}\mathrm{C}},

which results in R_str,areal = 0.279 cm² K/W. This particular resistance can now be used to find the Q_s & ΔT_sys values using the \gamma =\mathrm{0.9} master curves and a heat flux frontier curve can be generated as denoted with green dotted lines in Fig. 14.

A more detailed optimization approach is to utilize Eq. (12). Since Eq. (12) is defined per leg, the structural resistance can be multiplied by the number of elements to obtain the per leg structural resistance,

(17){{\displaystyle R}}_{\mathrm{str},\mathrm{per}\hspace{0.17em}\mathrm{leg}}={{\displaystyle R}}_{\mathrm{str}}\times {{\displaystyle N}}_{\mathrm{T}\mathrm{E}}

resulting in R_sink = 204.2 K/W and R_source = 23.7 K/W per TE leg. Similarly, the Q_s in Eq. (12) can be calculated as:

(18){{\displaystyle Q}}_{\mathrm{s}}={\displaystyle \frac{q^{\text{'}\text{'}}{{\displaystyle A}}_{\mathrm{T}\mathrm{E}\mathrm{C}}}{{{\displaystyle N}}_{\mathrm{T}\mathrm{E}}}},

which gives Q_s = 0.06127 W per leg. These values can now be substituted in Eq. (12), and using a multi-variable optimization method such as conjugate gradient method, the TE thickness and electrical current can be optimized to obtain the minimum source temperature. For reader’s convenience, most of the common programming software include canned multivariable optimization tools that can be easily utilized for such optimization.

Figure 14(a) illustrates the Pareto frontier curve for the discussed structural architecture, and Fig. 14(b) shows the optimum design variables, L and I, that generate the Pareto frontier. All three methods, analytical optimization, master curves and the simulation results have very good agreement with each other. The advantage of going through the optimization process reveals the maximum achievable cooling for the given conditions. In this case, the optimum thickness and electrical current for cooling of 50 W/cm² are found to be 100 microns and 2.8 A respectively (see Fig. 14(b)), which result in a maximum ΔT_sys of 43 K at the 50W/cm² (see Fig. 14(a)). Meaning that, any other thickness would yield lower ΔT_sys for the given system architecture at the given heat dissipation level. By relying on the maximum cooling fluxes of ultra-thin film TECs, which are considerably higher than thicker devices, and not performing the optimization procedure can mislead to wrong design decisions. The above optimization study shows, the optimum thickness, even for high flux applications, could be much larger than the thickness of common ultra-thin film TECs and in fact yield much greater ΔT_sys. For instance, if a TEC with 20 µm TE thickness (I_opt = 3.7 A) was utilized for this case study, only ΔT_sys = 11 K could be achieved at 50W/cm², which in fact is significantly lower than the ΔT_sys achieved via 100 microns. Another substantial benefit of going through the optimization procedure is to recognize if the targeted cooling is technically not attainable. For example, if a ΔT_sys = 60 at 50 W/cm² was targeted in this case study, it is obvious from the Pareto frontier in Fig. 14(a) that the intersection of ΔT_sys = 60 K at 50 W/cm² lies outside the Pareto frontier. Thus, unless the structural resistances were further minimized (higher HTC, fewer solid layers, lower contact resistances, etc.), or the TE material properties were improved, such target is beyond the capabilities of thermoelectric cooling.

Conclusions

In this paper, two interrelated subjects in thermoelectric cooler optimization are introduced and evaluated. First, the heat flux dependency of optimum thermoelectric element thickness and optimum current is demonstrated through the establishment of a Pareto frontier load curve. The frontier curve shows the amount of achievable system-level ΔT at any given source heat flux. Thus, it is very useful to understand the limitations of thermoelectric cooling in a particular architecture. It benefits the designers to understand what values of thickness and electrical current can provide the necessary cooling, or shows when the desired source temperatures at the given heat fluxes are not possible.

Second take away from this study is that the shape and bounds of the frontier curve heavily depend on certain system level parameters, such as structural thermal/electrical parasitics. The parasitics significantly affect the optimum thickness and electrical current, which in turn impacts the frontier curve. Therefore the thermoelectric phenomena is analytically evaluated in the presence of system level parasitics and a comprehensive equation is derived, which is later used in the optimization. The analytical model results are compared with numerical results using the commercially available FEM software Ansys Workbench. A very strong agreement is obtained between the two models, with a maximum discrepancy within 0.2 K. Using this analytical model, a wide optimization study is performed and 3 pairs of master curves are obtained at T_sink = 300 K and 400 K. The master curves are the links between the effects of the structural thermal resistances and the Pareto frontier curve. Once the structural resistance of a particular application is known, the master curves can be used to form the appropriate frontier curve. The formed frontier curve illustrates the limitations of thermoelectric cooling for that particular application. This was finally demonstrated via a case study where the geometry and boundary conditions are explained in detail. Both simulation and analytical optimization is used along with the values obtained graphically from the master curves, and the Pareto frontier formation is demonstrated.

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