Impact of thermal processes on multi-crystalline silicon

Abstract

Fabrication of modern multi-crystalline silicon solar cells involves multiple processes that are thermally intensive. These include emitter diffusion, thermal oxidation and firing of the metal contacts. This paper illustrates the variation and potential effects upon recombination in the wafers due to these thermal processes. The use of light emitter diffusions more compatible with selective emitter designs had a more detrimental effect on the bulk lifetime of the silicon than that of heavier diffusions compatible with a homogenous emitter design and screen-printed contacts. This was primarily due to a reduced effectiveness of gettering for the light emitter. This reduction in lifetime could be mitigated through the use of a dedicated gettering process applied before emitter diffusion. Thermal oxidations could greatly improve surface passivation in the intra-grain regions, with the higher temperatures yielding the highest quality surface passivation. However, the higher temperatures also led to an increase in bulk recombination either due to a reduced effectiveness of gettering, or due to the presence of a thicker oxide layer, which may interrupt hydrogen passivation. The effects of fast firing were separated into thermal effects and hydrogenation effects. While hydrogen can passivate defects hence improving the performance, thermal effects during fast firing can dissolve precipitating impurities such as iron or de-getter impurities hence lower the performance, leading to a poisoning of the intra-grain regions.

Keywords

gettering / grain boundaries / hydrogen / impurities / oxidation / passivation / solar cell

Introduction

The cost of silicon solar cell production has been decreasing over the last ten years. This has been driven by improvements in cell technology (higher efficiency) and reductions in the cost of the silicon material and cell processing [ 1]. The most common type of silicon currently used in manufacturing is p-type multi-crystalline (mc-Si) wafers [ 1]. These substrates are favored due to the low material cost and square shape, which enable larger active area fractions when incorporated into modules. While mono-crystalline solar cells have a slight performance advantage, the higher material cost means that multi-crystalline has tended to perform better in terms of price per watt ($/W). Recently, two new world records were achieved for multi-crystalline silicon solar cells, with efficiencies of 20.76% and 21.25% [ 2] demonstrating the potential of these low cost substrates. It is likely however that these remarkable cell efficiencies were only achieved on the highest quality wafers, which typically represent a small fraction of the total brick. In reality, the bulk of multi-crystalline wafers contain a distribution of defects and impurities, which need special processing to ensure they do not dominate the cell performance. The recent introduction of high-performance multi-crystalline silicon (HP mc-Si) has reduced this somewhat, however it remains important to study how the latest high efficiency processes interact with these recombination centers, and to develop effective characterization techniques to study their impact.

There have been several key factors contributing to the recent increase in cell efficiency: HP mc-Si silicon wafers [ 3], lighter emitter doping enabled by improved front side Ag pastes [ 4] and improved rear surface structures such as that of the passivated emitter, rear contact (PERC) solar cell [ 5]. The development of improved metallisation pastes has allowed for a better optimisation between losses due to contact resistance and surface recombination. This has led to the use of progressively more lightly doped emitters, which work well on mono-crystalline substrates but may have implications for the gettering efficiency on cheaper substrates [ 6]. Higher efficiencies may also be achieved by passivating these lightly doped emitters with a thermally grown oxide layer, while good for surface passivation, may result in increased poisoning of the substrate via the release of previously gettered impurities [ 7, 8]. Similarly, the PERC solar cell technology has improved the efficiency of industrially produced silicon solar cells using mc-Si wafers [ 1]. In this case, the new cell architecture introduces an additional source of hydrogen onto the rear surface, which may have implications for defect passivation if used effectively.

Many of the processes used to fabricate wafer based silicon solar cells involve high temperature processes, typically above 800°C. Mc-Si is known to be influenced by any thermal processes and such treatments can either harm or improve the resulting device’s performance [ 9, 10]. Difference types of mc-Si can also give different response to same process [ 7]. Furthermore, some defects such as dislocation clusters within mc-Si can limit the efficacy of phosphorus gettering during emitter formation by POCl₃ diffusion in a quartz tube furnace [ 11, 12].

Another critical process in fabrication of photovoltaic devices is the deposition of a hydrogenated silicon nitride (SiN_x:H) layer on the front surface to act as an anti-reflection coating and as a passivation layer to reduce surface recombination characteristics. Another benefit of this layer is that the SiN_x:H can act as a source of hydrogen. During the SiN_x:H layer deposition process, hydrogen is trapped in the SiN_x:H layer and the subsequent high temperature firing process then allows the hydrogen to diffuse into the bulk region of the wafer where it is able to passivate the defects in the silicon such as interstitial iron [ 13]. This can effectively improve the performance of the silicon solar cell, although a dissolution of impurities can occur simultaneously during the high temperature process [ 14, 15].

In this work, the key high temperature processes for state of the art mc-Si solar cell fabrication are investigated. These processes include POCl₃ diffusion, thermal oxidation, and rapid high temperature firing of the contacts. Experimental work is carried out on mono-crystalline and multi-crystalline silicon wafers in order to determine the impact of the presence of different types of impurities or defects. The presence of oxide layers is investigated along with the impact of phosphorus gettering and fast firing, which may enable hydrogenation from SiN_x:H layer or cause impurity dissolution. The interaction between these processes in modern solar cells is then investigated.

Methodology

The impact of thermal processes on mc-Si wafers was studied by creating a variety of symmetric test structures. The samples were characterized using typical lifetime techniques. The results were analyzed by dividing the wafers spatially into regions of relative good quality (i.e. the central region of the wafer) and poor regions close to the edge. These results were also compared to identical processing on high quality mono-crystalline substrates.

Sample preparation

Symmetric lifetime test structures were fabricated on industrial p-type 156 mm × 156 mm wafers. The wafers used were from three different sources: 1.6 W·cm mono-crystalline Czochralski Silicon (c-Si), 1.3 W·cm standard multi-crystalline silicon (mc-Si) and 1.3 W·cm high performance multi-crystalline silicon (HP mc-Si). All of the samples were chemically etched to remove the saw damage and form a standard texture on the surface. In the case of c-Si an alkaline solution was used to form random upright pyramids. The standard mc-Si and HP mc-Si were etched in a cooled isotropic etch to form an isotextured surface. After etching, half of the samples had a heavy phosphorus emitter diffusion applied to getter impurities in the bulk of the silicon. These samples were processed in a tube furnace for 25 min at 800°C in a POCl₃ ambient followed by a drive in for 40 min at 880°C in N₂ ambient. This thermal process was followed by a subsequent chemical etch in HF to remove phosphosilicate glass (PSG) from the wafer surface. Subsequently, the wafers were exposed to an alkaline solution (identical to that used to texture the c-Si samples) to remove the gettering diffusion and impurities within this region. In the results section these substrates are identified as “pre-gettered.”

Samples were then split and subjected to one of two emitter diffusion processes. A heavy emitter was created by phosphorus diffusion at 795°C with 425 sccm POCl₃ and 600 sccm O₂ for 25 min for PSG growth, followed by a drive in process that was done at 880°C with 7.5 L of N₂ for 40 min. This was to create a diffusion profile compatible with screen-printed contacts and a homogenous emitter. A light emitter was formed by phosphorus diffusion at 770°C with 400 POCl₃, 600 sccm O₂, 6.2 slm N₂ for 25 min for PSG growth, followed by a thermal process of 850°C with 7.5 L of N₂ for 25 min to further diffuse the phosphorus dopants into the silicon and approximately define the sheet resistance. Finally, a further high temperature drive in process was carried out at 880°C with 5 L O₂ for 40 min to redistribute dopants within the emitter. This light diffusion was representative of the passivated region of a selective emitter design with a surface concentration<1 × 10²⁰/cm³ that is not compatible with screen printed contacts. After diffusion, the PSG was removed in dilute HF.

Subsequently, lightly diffused samples underwent either annealing from 700°C to 890°C with 7 slm O₂ for 15 min or annealing process at 890°C with N₂ ambient to distinguish the impact of oxidation and thermal effects at this temperature. One sample did not have the thermal process as a control. One group of HP mc-Si wafers that underwent annealing at 890°C in oxygen, had a 2% HF dip to remove SiO₂ layer. On the other group investigating different thermal processes, the oxide layers were left on the surface.

A variety of combinations of surface passivation and rapid thermal processing were then applied to the samples. Rapid thermal processing consisted of heating the substrates to a peak temperature of 800°C with 2 s above 700°C using a belt firing furnace. The surface passivation applied at various stages consisted of a 75 nm layer of SiN_x:H (refractive index of 2.08 at 633 nm wavelength) deposited on both sides using a plasma-enhanced chemical vapor deposition system. In some cases the HP mc-Si samples were etched in a solution of 5% HF for 30 min to remove an existing SiN_x:H surface layer before re-deposition of the same layer. This was done to achieve similar surface passivation quality independent of the thermal processing applied. The full process flow for sample preparation is illustrated in Fig. 1.

Characterization

The impact of thermal processes on mono- and multi-crystalline silicon wafers was analyzed using electrochemical capacitance-voltage measurement to determine the profile of electrically active dopants in the emitter as shown in Fig. 2. The ECV profile provided good evidence of how the oxidation process varied the emitter profile as well as the emitter recombination. Sheet resistance was also measured using sheRRescan.

Samples were characterized using measurements of the effective lifetime after various stages of processing. Area averaged measurements of the effective minority carrier lifetime versus excess minority carrier density were measured using photo conductance testing with a Sinton WCT-120 [ 16]. The measured data was analyzed using the generalized technique with intrinsic Auger recombination removed using the Richter model [ 17]. The dark saturation current J₀,which relates to the recombination rate of the surface, was then extracted using the Kane-Swanson method [ 18].The bulk lifetime was determined by removing the surface and Auger lifetimes from the effective lifetime.

Spatially resolved lifetime data was measured using photoluminescence (PL) imaging with a commercial BTi R1 imaging tool [ 19]. A point spread function (PSF) deconvolution process was applied to all images in order to improve accuracy by reducing the artificial blurring effect caused by photon smearing in the tool’s detector. The deconvolution was carried out using the Matlab based PL Pro software with a PSF specifically determined for the BTi R1 system using the backward substitution method recently demonstrated by Teal and Juhl [ 20]. For each sample, PL images were taken at various processing stages and images were compared using the ICARUS software, which uses standard image registration algorithms to automatically align two images, allowing for one to be accurately subtracted from the other. This results in a difference map that highlights any changes caused by sample processing.

Results and discussion

Doping profiles

Figure 2 presents active phosphorous concentration as a function of depth from silicon surface as measured using ECV for the range of wafers with different oxidation condition. An increase in oxidation temperature led to a reduction in the surface concentration although the oxidation temperature below 850°C was not effective to reduce the peak concentration. As shown in Fig. 2, only annealing above 800°C showed significant drop in peak concentration. Junction depth, however, did not show significant correlation to the annealing temperatures. The sheet resistances of the samples are presented in Table 1. Higher oxidation temperature increased the sheet resistance of the emitters, which shows how the emitters became lighter. However, for oxidation below 800°C, similar sheet resistances were obtained. This indicates that the oxidation process was only effective at modulating the sheet resistance of the emitters for oxidation temperatures above 800°C. A comparison of N₂ annealing at 890°C to oxidation at 890°C was also performed. Both N₂ annealing and oxidation increased the sheet resistance, however, oxidation led to a more significant increase in the sheet resistance of the emitter. The response in bulk and surface region in these wafers with difference in doping profiles due to different annealing processes will be discussed.

Surface

Increasing oxidation temperature was shown to result in a reduction in the extracted J₀ value as shown in Fig. 3. As shown in Fig. 4, Mc-Si was analyzed in two different regions: impurities affected zone and the unaffected region, in which photoluminescence image of multi-crystalline wafer to indicate the regional difference across the wafer, circled in green indicates the unaffected region and circled in yellow indicates the impurity affected zone. In general, J₀ is decreased for samples annealed in oxygen and tends to decrease further for higher temperature oxidations on both mono- and multi-crystalline silicon wafers. The decrease in J₀ with increasing oxidation temperature may be explained by an improvement in surface passivation from the oxide layer or a reduction in recombination in the emitter itself. It has been widely reported that the quality of a thin oxide increases markedly with increasing oxidation temperature [ 21]. This indicates that the use of a high temperature oxidation step can grow an oxide layer that provides superior passivation to nitride alone and that the increase in passivation scales with temperature.

Two different regions within the mc-Si wafers were compared after firing. While firing has reduced the J₀ of the low impurity region, J₀ has increased in the high impurity concentration region. Mono-crystalline silicon wafers, which were used as a control also had lower J₀ after firing. This may indicate that the Shockley-Read-hall recombination, recombination due to presence of impurities within the emitter may have increased, possibly as a result of lower phosphorous concentrations leading to less precipitation sites. The gettering effect occurs in bulk region simultaneously such that if gettering has been less effective, the impurities should be present not only in the emitter but in the bulk as well. This will be investigated in the next section.

Bulk silicon region and impact of firing

In addition, the effects upon the emitter the oxidation processes also had a substantial impact on bulk recombination. It may be seen in Fig. 5 that bulk lifetime was affected as oxidation temperature was increased. Initially, there were no significant differences in the bulk lifetime with different oxidation processes across the mc-Si wafers before fast firing was done. However, after firing, the wafers that were oxidised at higher temperature exhibited lower bulk lifetime characteristics in Fig. 5.

The trend of lower bulk lifetime at higher oxidation temperature was also shown on mono-crystalline silicon wafers. Comparing the bulk lifetime after oxidation at 890°C to the bulk lifetime with annealing at 890°C or with no annealing, bulk lifetime with no annealing had highest bulk lifetime while bulk lifetime with oxidation at 890°C is the lowest. One possible explanation for this is that the higher temperatures processes released more impurities from grain boundaries however in this case it would be expected that the sample annealed in nitrogen should have shown a similar drop in bulk lifetime. An alternative explanation is that the oxide layer, that would only be present on wafers with oxidation, may have interrupted the hydrogen passivation by reducing diffusion from the nitride layer into the silicon. As higher oxidation temperatures would form thicker oxide layers, these layers would likely have a more significant hydrogen blocking effect which agrees with the observed results.

Another explanation is that, as oxidation and annealing reduced the emitter doping concentration, this in turn could reduce the emitter gettering effect so that during firing impurities may have been more effectively diffused back into the bulk. This effect could be further exacerbated by a decrease in gettering effectiveness with temperature [ 22] due to an alteration in the ratio of trapping and release of impurities at gettering sites. This could explain why the bulk lifetime was lower in the sample oxidised at 800°C despite the emitter profile being very similar to those oxidised at 700°C or 750°C. The PL images taken before firing in Fig. 6 shows improvements due to the oxidation process. The intra-grain regions appear to be brighter with higher temperature. Annealing in nitrogen ambient at 890°C also showed an improvement although it was not as effective as the oxidation at 890°C. The improvement by annealing in nitrogen ambient may be due to redistribution of the phosphorus as peak concentration at the surface is reduced comparing to the concentration of sample with no annealing. The low PL counts on non-annealed sample are most likely due to surface recombination, as this sample did not have any thermal treatment on the surface.

The PL images in Fig. 7 indicate that the improvement after firing was shown to be mostly along the grain boundaries. However this improvement decreased with oxidation temperature, not do only grain boundaries appear more clearly on the PL images of wafers oxidised at higher temperatures, but the bulk lifetime of this region was also reduced when comparing to other samples with different annealing conditions. Samples processed at lower oxidation temperatures and those with no annealing showed less recombination at grain boundaries. As hydrogen passivation due to firing is known to be effective along the grain boundaries [ 23], the results support the explanation that the hydrogen passivation may have been interrupted by the oxide layer as the samples with higher oxidation temperature, and hence thicker oxide layers have more grain boundaries appearing on the PL images than the samples with lower oxidation temperature, or no annealing after firing. The sample with annealing in nitrogen ambient also had a relatively significant amount of recombination at grain boundaries after firing which indicates that there is also a thermal impact on dissolving precipitated impurities along grain boundaries. The sample with no annealing showed little or no recombination at grain boundaries in the PL image. In comparison to annealing at 890°C either in oxygen or in nitrogen, this suggests that both hydrogen blocking and dissolution of precipitated impurities along grain boundaries were minimised.

The results on surface and bulk have demonstrated that gettering is important, particularly in the impurity affected zone, however it is not possible from these results to clearly distinguish between less effective gettering and hydrogen blocking. Therefore, in the next section, the impact of phosphorus pre-gettering will be discussed to isolate these two impacts.

Impact of phosphorus pre-gettering

The response of the multi-crystalline silicon wafers with heavy and light diffusion to a pre-gettering process is presented in Fig. 8. As phosphorus gettering is effective to getter the impurities from the bulk to surface, the bulk lifetime of the wafers was compared. The phosphorus pre-gettering process was carried out to remove impurities from the bulk of the silicon. However, since the diffusion was performed at a high temperature process with a long duration, a potential “poisoning” effect on the wafers is possible. The bulk lifetimes of wafers with and without a pre-gettering process was compared on samples with a heavy diffusion and light diffusion. The relative change in bulk lifetime was more significant on lightly diffused wafers, with pre-gettering leading to a substantial increase in bulk lifetime as shown in Fig. 8. In contrast, no observable change in bulk lifetime was noted for the heavily diffused samples with or without pre-gettering.

A comparison of PL images (see Fig. 9) highlighted potential reasons for the increased effectiveness of the light diffusion. Ratio in Fig. 9 shows how much the PL counts have multiplied or divided by when two PL images were overlayed and compared. Pre-gettered and non-gettered wafers for each diffusion were overlayed and compared to see the regional improvement or the regional reduction. There were both minor increases and moderate reduction in PL counts across the heavily diffused sample. Therefore, the overall change in lifetime was not significant. However, lightly diffused samples demonstrated a greater improvement in PL response through the addition of a pre-gettering process, especially within the grains. This indicates the light diffusion by itself may not getter impurities effectively. Subsequently, with the industry trend tending toward the use of lighter emitters, multi-crystalline silicon wafers may suffer from less effective gettering during the emitter diffusion process. Furthermore, a potential release of impurities from lightly diffused wafers may occur during firing with some studies already showing this effect [ 14]. In the next section, response of the remaining impurities to fast firing and hydrogen introduction will be discussed.

Impact of hydrogenation versus impact of thermal annealing during firing

Firing with the presence of SiN_x:H layer allows the hydrogen from the silicon nitride layer to penetrate into the bulk and passivate defects. Firing processes were performed on samples with and without SiN_x:H present. This isolated thermal effects during firing from hydrogen passivation effects. Due to the inhomogeneity of multi-crystalline silicon wafers, only high lifetime region was analyzed in Fig. 10. Regardless of whether the wafer was pre-gettered or not, the response of HP mc-Si samples to firing with and without SiN_x: H presence was similar. The highest PL response was observed on both pre-gettered and non-gettered samples fired in the presence of SiN_x: H (see Fig. 10(d-1) & Fig. 10(d-2)). This indicates that hydrogen plays a key role in determining the lifetime of the sample. Furthermore, samples fired without SiN_x:H show a reduced PL response in many areas, indicating a detrimental thermal effect. The deposition of the SiN_x:H (see Fig. 10(b-1) & Fig. 10(b-2)) also had a slightly detrimental effect on minority carrier lifetime compared to the control sample. Similar experiments were performed in a previous study and the fast firing was not observed to have any detrimental effect on monocrystalline silicon wafers [ 24]. The change trends in the PL response of the samples in Fig. 10 are correlated to changes in the bulk lifetime of the silicon (see Fig. 11).

The results in Fig. 10 clearly indicate that the competition between hydrogen passivation of defects during firing and dissolution of impurities. Comparing non-gettered samples to pre-gettered ones, the pre-gettered samples showed the most improvement from firing process with SiN_x: H in the high lifetime regions. This suggests that hydrogen passivation is more effective with less impurities, in agreement with previous studies [ 25]. This may be due to the higher concentration of hydrogen relative to the number of defects, or due to the dissolution of impurities playing a reduced role. In contrast although the pre-gettered dislocation cluster region had higher lifetime than non-gettered dislocation cluster region prior to firing, after firing with SiN_x:H the pre-gettered dislocation cluster region showed a sharp drop in bulk lifetime (120 µs to 70 µs). In this case it might be concluded that due to the higher impurity and defect concentrations the hydrogen passivation process was less effective than the dissolution process.

Conclusions

The impact of thermal processes including emitter diffusion, thermal oxidation and fast-firing on multi-crystalline and mono-crystalline silicon wafers were analyzed. Oxidation processes were observed to substantially change the diffusion profile, particularly with increasing oxidation temperatures. The quality of surface passivation was greatly enhanced by the presence of thermal oxide layers on both types of wafers. The observed J₀ was lowest for the highest oxidation temperature, potentially due to the growth of a thicker and higher quality oxide. However, such processes appear to detrimentally affect subsequent hydrogen passivation, either by interrupting the hydrogen passivation or by releasing the impurities into bulk. Firing the wafers through a belt-furnace provided an additional improvement in surface characteristics, but J₀ increased in regions with high impurity concentrations on multi-crystalline silicon wafers. This could indicate that the inactive impurities were activated during firing or that some impurities that were trapped in the grain boundaries may have diffused into the grains.

The wafer with highest oxidation temperature had the lowest bulk lifetimes, which would indicate that the grown oxide layer may detrimentally block hydrogen in-diffusion from the SiN_x:H and prevent hydrogenation. The c-Si and mc-Si wafers with annealing at the same temperature had higher bulk lifetime after firing when they initially had similar bulk lifetimes. Pre-gettered wafers experienced greater improvement within the bulk region after firing with SiN_x:H layer. This indicates a possible de-gettering effect during firing with a lightly diffused emitter. HP mc-Si wafers fired without a SiN_x:H layer experienced a decrease in bulk lifetime in high lifetime regions indicating that firing can poison the bulk. This suggests that optimisation is required between improvements from hydrogen passivation and losses from thermal impact. The effectiveness of gettering was also compared on lightly and heavily diffused emitters. It was observed that lightly diffused emitters suffered from reduced bulk lifetimes compared to those of heavily diffused emitters, although a prior gettering process used in conjunction with lightly diffused emitters could yield substantially higher bulk lifetimes than using heavily diffused emitters alone. Furthermore, the same pre-gettering process used in conjunction with heavily diffused emitters did not enhance bulk lifetime.

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