RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb

Abstract

The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field. To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs. However, due to constraints in cost and performance, the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems. By exploring the RISC-V and ARM Thumb ISAs, this paper proposes RVAM16, which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique. The results show that, when running non-native ARM Thumb programs, RVAM16 achieves a significant speedup of over 2.73× with less area and energy consumption compared to using hardware binary translation alone, reaching more than 70% of the performance of native RISC-V programs.

Graphical abstract

Keywords

multiple-ISA processor / architecture / binary translation / RISC-V / embedded

Libo Huang received his BS and PhD degree in computer engineering from National University of Defense Technology, China in 2005 and 2010, respectively. He is a professor at College of Computer Science and Technology, National University of Defense Technology, China. His research interests include computer architecture, hardware/software co-design, VLSI design, and on-chip communication

Jing Zhang received his BS degree in electronic commerce from Northwest Agriculture and Forestry University, China in 2020. He is a Master student at College of Computer Science and Technology, National University of Defense Technology, China. His research interests include microprocessor architecture and AI accelerator

Ling Yang received his BS degree in integrated circuit design and integrated systems from Chongqing University, China in 2020, and MS degree in electronic science and technology from National University of Defense Technology, China in 2022. He is a PhD candidate at College of Computer Science and Technology, National University of Defense Technology, China. His research interests include microprocessor architecture

Sheng Ma received his BS and PhD degree in computer science and technology from National University of Defense Technology, China in 2007 and 2012, respectively. He is a professor at College of Computer Science and Technology, National University of Defense Technology, China. His research interests include on-chip networks and SIMD architecture

Yongwen Wang received his PhD degree in computer science from National University of Defense Technology, China in 2004. He is a professor at College of Computer Science and Technology, National University of Defense Technology, China. His research interests include computer architecture and high performance computing

Yuanhu Cheng received his BS degree in computer science and technology from Sichuan University, China in 2018, and MS degree in computer science and technology from National University of Defense Technology, China in 2021. His research interests include microprocessor architecture

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 62272475, 62090023, and 62172430), the National Key R&D Program of China (No. 2021YFB0300300), the Natural Science Foundation of Hunan Province of China (Nos. 2022JJ10064 and 2021JJ10052), the STIP of Hunan Province (No. 2022RC3065), and the Key Laboratory of Advanced Microprocessor Chips and Systems.

Competing interests

The authors declare that they have no competing interests or financial conflicts to disclose.

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