RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb

Abstract

The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field. To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs. However, due to constraints in cost and performance, the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems. By exploring the RISC-V and ARM Thumb ISAs, this paper proposes RVAM16, which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique. The results show that, when running non-native ARM Thumb programs, RVAM16 achieves a significant speedup of over 2.73× with less area and energy consumption compared to using hardware binary translation alone, reaching more than 70% of the performance of native RISC-V programs.

Graphical abstract

Keywords

multiple-ISA processor / architecture / binary translation / RISC-V / embedded

References

[1] Adegbija T, Rogacs A, Patel C, Gordon-Ross A. Microprocessor optimizations for the internet of things: a survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37( 1): 7–20

[2] Saso K, Hara-Azumi Y. Simple instruction-set computer for area and energy-sensitive IoT edge devices. In: Proceedings of the 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). 2018, 1−4

[3] Saso K, Hara-Azumi Y. Revisiting simple and energy efficient embedded processor designs toward the edge computing. IEEE Embedded Systems Letters, 2020, 12( 2): 45–49

[4] Sites R L, Chernoff A, Kirk M B, Marks M P, Robinson S G. Binary translation. Communications of the ACM, 1993, 36( 2): 69–81

[5] Apple Inc. About the Rosetta translation environment. See developer.apple.com/documentation/apple-silicon/about-the-rosetta-translation-environment website, Accessed: 2023

[6] Bellard F. QEMU, a fast and portable dynamic translator. In: Proceedings of the USENIX Annual Technical Conference. 2005, 41−46

[7] Hong D Y, Hsu C C, Yew P C, Wu J J, Hsu W C, Liu P, Wang C M, Chung Y C. HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores. In: Proceedings of the 10th International Symposium on Code Generation and Optimization. 2012, 104−113

[8] Ilbeyi B, Lockhart D, Batten C. Pydgin for RISC-V: a fast and productive instruction-set simulator. In: Proceedings of the 3rd RISC-V Workshop. 2016

[9] Clark M, Hoult B. rv8: a high performance RISC-V to x86 binary translator. In: Proceedings of the 1st Workshop on Computer Architecture Research with RISC-V (CARRV). 2017

[10] Sabri C, Kriaa L, Azzouz S L. Comparison of IoT constrained devices operating systems: a survey. In: Proceedings of the 14th International Conference on Computer Systems and Applications (AICCSA). 2017, 369−375

[11] Shen B Y, Chen J Y, Hsu W C, Yang W. LLBT: an LLVM-based static binary translator. In: Proceedings of 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 2012, 51−60

[12] Lupori L, Rosario V, Borin E. Towards a high-performance RISC-V emulator. In: Proceedings of 2018 Symposium on High Performance Computing Systems (WSCAD). 2018, 213−220

[13] Venkat A, Tullsen D M. Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor. In: Proceedings of the 41st International Symposium on Computer Architecture (ISCA). 2014, 121−132

[14] Venkat A, Basavaraj H, Tullsen D M. Composite-ISA cores: enabling multi-ISA heterogeneity using a single ISA. In: Proceedings of 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). 2019, 42−55

[15] Balkind J, Lim K, Schaffner M, Gao F, Chirkov G, Li A, Lavrov A, Nguyen T M, Fu Y, Zaruba F, Gulati K, Benini L, Wentzlaff D. BYOC: a ”bring your own core” framework for heterogeneous-ISA research. In: Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems. 2020, 699−714

[16] Rokicki S, Rohou E, Derrien S. Hybrid-DBT: hardware/software dynamic binary translation targeting VLIW. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38( 10): 1872–1885

[17] Capella F M, Brandalero M, Carro L, Beck A C S. A multiple-ISA reconfigurable architecture. Design Automation for Embedded Systems, 2015, 19( 4): 329–344

[18] Fajardo J, Rutzig M B, Carro L, Beck A C S. Towards a multiple-ISA embedded system. Journal of Systems Architecture, 2013, 59( 2): 103–119

[19] Chai K, Wolff F, Papachristou C. XBT: FPGA accelerated binary translation. In: Proceedings of IEEE National Aerospace and Electronics Conference. 2021, 365−372

[20] Rokicki S, Rohou E, Derrien S. Hardware-accelerated dynamic binary translation. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE). 2017, 1062−1067

[21] Waterman A, Asanovic K. The RISC-V instruction set manual: volume I: unprivileged ISA. 2019

[22] ARM. ARM^® Cortex^®-M0 DesignStart^TM RTL Testbench: user guide . 2015

[23] Wang W, Liu X, Yu J, Li J, Mao Z, Li Z, Ding C, Zhang C. The design and building of openKylin on RISC-V architecture. In: Proceedings of the 15th International Conference on Advanced Computer Theory and Engineering (ICACTE). 2022, 88−91

RIGHTS & PERMISSIONS

Higher Education Press