Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system

Abstract

In this paper, a new model based on an improved Brent Kung (BK) parallel prefix network (PPN) algorithm is proposed and realized in the field programmable gate array (FPGA). This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying (DQPSK) precoder in 40 Gb/s polarization division multiplex (PolDM) DQPSK system. In the computation process, the computation complexity (area) optimization with fan-out limited is achieved. In the implementation, 770 FPGA slice registers are utilized, which save about 60% logic resources compared with the previous Kogge Stone (KS) algorithm.

Keywords

Field Programmable Gate Array / Carrier Phase / Computation Unit / Polarization Mode Dispersion / Logic Resource

References

[1] WinterM., SettiD., PetermannK.. IEEE Photonics Technology Letters, 2010, 22: 538

[2] MaH., BaoH., WangS., JinZ.. Journal of Optoelectronics Laser, 2009, 20: 1029

[3] ZhangZ., NieY., SangM., KuangQ., YeZ.. Journal of Optoelectronics Laser, 2009, 20: 863

[4] Y. Konishi, K. Ishida, K. Kubo and T. Mizuochi, Optical Fiber Communication Conference and Exposition, OThR3 (2006).

[5] T. Han and D. A. Carlson, Proc. 8th Symp. Computer Arithmetic, 49 (1987).

[6] L. Zhou, Y. Huang, Y. Zhang, G. Wang, M. Zhang, J. Zhang and X. Yuang, International Forum on Information Technology and Applications, Kunming, China, 2010.

[7] L. Zhou, Y. Zhang, G. Wang, M. Zhang, J. Zhang, Y. Huang and L. Li, 12th International Conference on Transparent Optical Networks, Munich, Germany, 23 (2010).

[8] KoggeP. M., StoneH. S.. IEEE Trans. on Computers, 1973, C-22: 786