A unified approach of PID controller design for unstable processes with time delay

Abstract

This paper addresses a unified approach of the PID controller design for low as well as high order unstable processes with time delay. The design method is based on the direct synthesis (DS) approach to achieve the enhanced load disturbance rejection. To improve the servo response, a two-degree of freedom control scheme has been considered. A suitable guideline has been provided to select the desired reference model in the DS scheme. The direct synthesis controller has been approximated to the PID controller using the frequency response matching method. A consistently better performance has been obtained in comparison with the recently reported methods.

Keywords

unstable process / maximum sensitivity / time delay / higher order process / direct synthesis method / frequency response matching

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