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Abstract
As semiconductor technologies have been shrinking, the speed of circuits, integration density, and the number of I/O interfaces have been significantly increasing. As a consequence, electromagnetic emanation (EME) becomes a critical issue in digital system designs. Electronic devices must meet electromagnetic compatibility (EMC) requirements to ensure that they operate properly, and safely without interference. I/O buffers consume high currents when they operate. The bonding wires, and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference (EMI). Therefore, I/O switching activities significantly contribute to the EMI. In this paper, we evaluate and analyze the impact of I/O switching activities on the EME. We will change the circuit configurations such as the supply voltage for I/O banks, their switching frequency, driving current, and slew rate. Additionally, a trade-off between the switching frequencies and the number of simultaneous switching outputs (SSOs) is also considered in terms of EME. Moreover, we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns. The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations. All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.
Keywords
electromagnetic interference
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electromagnetic emanation
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near field emissions
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field programmable gate array
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slew rate
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Van Toan Nguyen, Minh Tung Dam, Jeong-Gun Lee.
Electromagnetic emanation exploration in FPGA-based digital design.
Journal of Central South University, 2019, 26(1): 158-167 DOI:10.1007/s11771-019-3990-1
| [1] |
PilsooL, JaeK L, KyooY L, InchaeS, BooG K. Analysis of EMI dependence on signal duty and supplied voltage [C]. IEEE Workshop on Signal Propagation on Interconnects, 2009, IEEE, Strasbourg: 14
|
| [2] |
KimN K, HwangJ S, KimS Y. EMI prediction of slew-rate controlled I/O buffers by full-wave and circuit Co-simulation [J]. Journal of Semiconductor Technology and Science, 2014, 14(4): 471-477
|
| [3] |
ChanR S, TanN F, MokhtarM R. Simultaneous switching noise impact to signal eye diagram on high-speed I/O [C]. 4th Asia Symp on Quality Electronic Design, 2012, IEEE, Penang: 200205
|
| [4] |
HaruyaF, YoI, ToshioS. Measurement and analysis of SSN and Jitter of FPGA [C]. 2012 Int Symp on Electromagnetic Compatibility, 2012, IEEE, Rome: 16
|
| [5] |
OikawaR, GopeD, JandhyalaV. Return-path extraction technique for SSO analysis of low-cost wire-bonding BGA packages [J]. IEEE Transaction on Components, Packaging and Manufacturing Technology, 2012, 2(4): 677-686
|
| [6] |
RamdaniM, SicardE, BoyerA, DhiasB, WhalenJ J, HubingT H, CoenenM, WadaO. The electromagnetic compatibility of integrated circuits-past, present, and future [J]. IEEE Transaction on Electromagnetic Compatibility, 2009, 51(1): 78-100
|
| [7] |
TakuyaS, KumpeiY, HidehiroT, KojiN, MakotoN. An extended direct power injection method for in-place susceptibility characterization of VLSI circuits against electromagnetic interference [J]. IEEE Transaction on VLSI Systems, 2015, 23(10): 2347-2351
|
| [8] |
LeeJ G. A low EMI circuit design with asynchronous multi-frequency clocking [J]. IEICE Transactions on Electron, 2014, E97-C(4): 1158-1161
|
| [9] |
KumarS, ChellappaS, ClarkL T. Temporal pulse-clocked multi-bit flip-flop mitigating SET and SET [C]. 2015 IEEE Int Symp on Circuits and Systems (ISCAS), 2015, IEEE, Lisbon: 814817
|
| [10] |
FujitaH, TakataniH, TanakaY, ShoheiK, MasaomiS, ToshioS. Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures [C]. 9th International Workshop on EMC of Integrated Circuit. Nara: IEEE, 2013142146
|
| [11] |
YasuhiroO, MasanoriH, ToshikiK, TakaoO. Supply noise suppression by triple-well structure [J]. IEEE Transaction on VLSI Systems, 2013, 21(4): 781-785
|
| [12] |
CarrJ JThe technician’s EMI handbook: Clues and solutions [M], 2000, Newnes, Massachusetts
|
| [13] |
ParkH H, JangH T, ParkH B, CheolseungC H. An EMI evaluation method for integrated circuits in mobile devices [J]. IEEE Transaction on Electromagnetic Compatibility, 2013, 55(4): 780-787
|
| [14] |
FangW-x, ShiC-l, ChenL-h, EnY-f, LiuY, XiaoQ-zhong. Near field characterization of the electromagnetic interference for a microcontroller [C]. 2014 Int Conference on Reliability, Maintainability and Safety (ICRMS), 2014, IEEE, Guangzhou: 3235
|
| [15] |
LecaJ P, FroidevauxN, DupreP, GillesJ, HenriB R. EMI measurement, modeling, and reduction of 32-Bit high-performance microcontrollers [J]. IEEE Transaction on Electromagnetic Compatibility, 2014, 56(5): 1035-1044
|
| [16] |
AlaeldineA, LacrampeN, BoyaerA, PerdriauR, GaignetF, RamdaniM, SicardE, DrissiM. Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits [J]. Elsevier Microelectronics Journal, 2008, 39: 1728-1735
|
| [17] |
GaoX, FangJ, ZhangY-j, HamedK, DavidP. Far-field prediction using only magnetic near-field scanning for EMI test [J]. IEEE Transaction on Electromagnetic Compatibility, 2014, 56(6): 1335-1343
|
| [18] |
DC and switching characteristics (Spartan-3 FPGA family Datasheet) [R]. San Jose: Xilinx Inc., 2013.
|
| [19] |
SwaminathanM, EnginA E. Power integrity modeling and design for semiconductors and systems [M]. Massachussetts: Prentice Hall, 2007
|
| [20] |
DengS, HubingT, BeetnerD. Analysis of chip-level EMI using near-field magnetic scanning [C]. 2004 Int Symp on Electromagnetic Compatibility, 2004, IEEE, Sendai: 174177
|