Impacts of NBTI/PBTI on power gated SRAM

Abstract

A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 10⁶ s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 10⁶ s working time compared with previous work.

Keywords

negative bias temperature instability (NBTI) / positive bias temperature instability (PBTI) / static random access memory (SRAM) / power gating

References

[1] SchroderD K, BabcockJ A. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing [J]. Journal of Applied Physics, 2003, 94(1): 1-18

[2] BernsteinK, FrankD J, GattikerA E, HaenschW, JiB L, NassifS R, NowakE J, PearsonD J, RohrerN J. High-performance CMOS variability in the 65-nm regime and beyond, IBM [J]. Res & Dev, 2006, 50(4/5): 433-450

[3] BansalA, RaoR, KimJ J, ZafarS, StathisJ H, ChuangC T. Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability [J]. Microelectronics Reliability, 2009, 49(6): 642-649

[4] ZafarS, KimY H, NarayananV, CabralC, ParuchuriV, DorisB, StathisJ, CallegariA, ChudzikM. A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates [C]. IEEE Symp VLSI Technol Dig Tech Paper. Hawaii, USA, 200623-25

[5] CalimeraA, MaciiE, PoncinoM. Analysis of NBTI-induced SNM degradation in power-gated SRAM cells [C]. ISCAS 2010: Preceeding of 2010 IEEE International Symposium on Circuits and Systems, 2010785-788

[6] YangH I, HuangW, ChuangC-Te. Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-k metal-gate devices [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 29(7): 1192-1204

[7] WangW. Compact modeling and simulation of circuit reliability for 65-nm CMOS technology [J]. IEEE Transactions on Device and Materials Reliability, 2007, 7(4): 509-517

[8] KumarS V. An analytical model for negative bias temperature instability [C]. ICCAD’06: IEEE/ACM international conference on Computer-aided design, 2006493-496

[9] BhardwayS, WangW-p, VatikondaR, CaoY, VrudhulaS. Predictive modeling of the NBTI effect for reliable design [C]. IEEE 2006 Custom Integrated Circuits Conference. San Jose, Carlifornia, USA, 2006189-192

[10] ShinJ, ZyubanV, BoseP. A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache SRAM lifetime [C]. Proc Int Symp Comput Architecture. Beijing, China, 2008353-362

[11] TiwariA, TorrellasJ. Facelift: Hiding and slowing down aging in multicores [C]. MICRO 2008: Proc Int Symp. Microarchitecture (MICRO), Como, Italy, 2008, 11: 129-140

[12] AbellaJ, VeraX, GonzalezA. Penelope: The NBTI-aware processor [C]. MICRO 2007: Proc Int Symp Microarchitecture. Chicago, USA, 200785-96

[13] KumarS V, KimC H, SapatnekarS S. Impact of NBTI on SRAM read stability and design for reliability [C]. Proc Int Symp Quality Electron Design. California, USA, 2006210-218

[14] Predictive Timing Model [EB/OL]. http://www.eas.asu.edu/~ptm/

[15] KangK, KufluogluH, RoyK. Impact of negativebias temperature instability in nanoscale SRAM array: Modeling and analysis [J]. IEEE Trans Comput-Aided Des Integr Syst, 2007, 26(10): 1770-1781

[16] LiY M, SkadronK, BrooksD, HuZ G. Performance, energy and thermal considerations for SMT and CMP architectures [C]. HPCA: The 11th International Symposium on High-performance Computer Architecture. San Francisco, USA, 200571-82

[17] SiddiquaT, GurumurthiS. Recovery boosting: A technique to enhance NBTI recovery in SRAM arrays [C]. IEEE Symposium on VLSI. Lixouri, Kefalonia, 2010393-398

[18] ZhangC YArchitectural level leakage power optimization for ultra-deep submicron microprocessors [D], 2006ChangshaNational University of Defense Technology

[19] KaxirasS, HuZ, MartonosiM. Cache decay: Exploiting generational behavior to reduce cache leakage power [C]. ISCA 2001: International Symposium of Computer Architecture. Gothenburg, Sweden, 2001240-251