Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

Abstract

A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

Keywords

eFuse / one-time programmable memory / 2-dimensional array

References

[1] KimJ. H., KimD. H., JinL. Y., HaP. B., KimY. H.. Design of 1 kb eFuse OTP memory ip with reliability considered [J]. Journal of Semiconductor Technology and Science, 2011, 11(2): 88-94

[2] KimD. H., JangJ. H., JinL. Y., LeeJ. H., HaP. B., KimY. H.. Design and measurement of a 1-kbit efuse one-time programmable memory ip based on a BCD process [J]. IEICE transaction on Electronics, 2010, E93.C(8): 1365-1370

[3] RobsonN., SafranJ., KothandaramanC., CesteroA., XiangC., RajeevakumarR., LeslieA., MoyD., KinhataT., IyerS.. Electrically programmable fuse (efuse): from memory redundancy to autonomic chips [C]. Proceeding of Custom integrated circuits conference, 2007San JoseIEEE Press799-804

[4] KulkamiS., ChenZ., HeJ., JiangL., PedersenB., ZhangK.. High-density 3-D metal-fuse prom featuring 1.37 μm² 1T1R bit cell in 32 nm high-k metal-gate CMOS technology [C]. 2009 Symposium on VLSI circuits, 2009HillsboroIEEE Press28-29

[5] KimJ. H., JangJ. H., JinL. Y., HaP. B., KimY. H.. Design of low-power OTP memory IP and its measurement [J]. Korean Institute of Maritime Information and Communication Sciences, 2010, 14(11): 2541-2547

[6] JangJ. H., JinL. Y., JeonH. G., KimK. I., HaP. B., KimY. H.. Design of an 8-bit differential paired eFuse OTP memory IP reducing sensing resistance by half [J]. Journal of Central South University, 2012, 19(1): 168-173

[7] KimM. S., YoonK. S., JangJ. H., JinL. Y., HaP. B., KimY. H.. Design of a 32-bit eFuse OTP memory for PMICs [J]. Korean Institute of Maritime Information and Communication Sciences, 2011, 15(10): 2209-2216