SS-SERA: An improved framework for architectural level soft error reliability analysis

Abstract

Integrated with an improved architectural vulnerability factor (AVF) computing model, a new architectural level soft error reliability analysis framework, SS-SERA (soft error reliability analysis based on SimpleScalar), was developed. SS-SERA was used to estimate the AVFs for various on-chip structures accurately. Experimental results show that the AVFs of issue queue (IQ), register update units (RUU), load store queue (LSQ) and functional unit (FU) are 38.11%, 22.17%, 23.05% and 24.43%, respectively. For address-based structures, i.e., level1 data cache (L1D), DTLB, level2 unified cache (L2U), level1 instruction cache (L1I) and ITLB, AVFs of their data arrays are 22.86%, 27.57%, 14.80%, 8.25% and 12.58%, lower than their tag arrays’ AVFs which are 30.01%, 28.89%, 17.69%, 10.26% and 13.84%, respectively. Furthermore, using the AVF values obtained with SS-SERA, a qualitative and quantitative analysis of the AVF variation and predictability was performed for the structures studied. Experimental results show that the AVF exhibits significant variations across different structures and workloads, and is influenced by multiple microarchitectural metrics and their interactions. Besides, AVFs of SPEC2K floating point programs exhibit better predictability than SPEC2K integer programs.

Keywords

soft error / architectural vulnerability factor (AVF) / AVF estimation model

References

[1] LiB., DuanL., PengL.. Efficient microarchitectural vulnerabilities prediction using boosted regression trees and patient rule inductions [J]. IEEE Transactions on Computers, 2010, 59(5): 593-607

[2] WangS., HuJ., ZiavrasS. G.. On the characterization and optimization of on-chip cache reliability against soft errors [J]. IEEE Transactions on Computers, 2009, 58(9): 1171-1184

[3] WangS., HuJ., ZiavrasS. G.. Self-adaptive data caches for soft-error reliability [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(8): 1503-1507

[4] ErginO., UnsalO. S., VeraX., GonzalezA.. Reducing soft errors through operand width aware policies [J]. IEEE Transactions on Dependable and Secure Computing, 2009, 6(3): 217-230

[5] YoonD. H., ErezM.. Memory mapped ecc: low-cost error protection for last level caches [C]. Proceedings of 36th International Symposium Computer Architecture, 2009New York, NY, USAACM116-127

[6] YoonD. H., ErezM.. Virtualized and flexible ECC for main memory [C]. Proceedings of the 15th Architectural Support for Programming Languages and Operating Systems, 2010New York, NY, USAACM397-408

[7] KimS.. Reducing area overhead for error-protecting large L2L3 caches [J]. IEEE Transactions on Computers, 2009, 58(3): 300-310

[8] SridharanV., AsadiH., TahooriM., KaeliD.. Reducing data cache susceptibility to soft errors [J]. IEEE Transactions on Dependable and Secure Computing, 2006, 3(4): 353-364

[9] MukherjeeS. S., WeaverC., EmerJ., ReinhardtS., AustinT.. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor [C]. Proceedings of the International Symposium on Microarchitecture, 2003Washington D C, USAIEEE Computer Society29-40

[10] WangN. J., QuekJ., RafaczT. M., PatelS. J.. Characterizing the effects of transient faults on a high-performance processor pipeline [C]. Proceedings of the International Conference on Dependable Systems and Networks, 2004Piscataway, NJ, USAIEEE61-70

[11] WalcottK. R., HumphreysG., GurumurthiS.. Dynamic prediction of architectural vulnerability from microarchitectural state [C]. Proceedings of the International Symposium on Computer Architecture, 2007New York, NY, USAACM516-527

[12] FuX., PoeJ., LiT., FortesJ.. Characterizing microarchitecture soft error vulnerability phase behavior [C]. Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2006Piscataway, NJ, USAIEEE147-155

[13] SoundararajanN., ParasharA., SivasubramaniamA.. Mechanisms for bounding vulnerabilities of processor structures [C]. Proceedings of the International Symposium on Computer Architecture, 2007New York, NY, USAACM506-515

[14] BiswasA., CheveresanR., EmerJ., MukherjeeS. S., RacunasP. B., RanganR.. Computing architectural vulnerability factors for address-based structures [C]. Proceedings of the International Symposium on Computer Architecture, 2005New York, NY, USAACM532-543

[15] FU X, LI T, FORTES J. Sim-SODA: A Framework for microarchitecture reliability analysis [C]// Proc of the Workshop on Modeling, Benchmarking and Simulation (Held in conjunction with International Symposium on Computer Architecture). 2006: 124–133.

[16] LiX., AdveS. V., BoseP., RiversJ. A.. SoftArch: An architecture-level tool for modeling and analyzing soft errors [C]. Proc of the Int Conf on Dependable Systems and Networks, 2005Piscataway, NJ, USAIEEE496-505

[17] BURGER D, AUSTIN T. The Simplescalar toolset, version 3.0 [EB/OL]. SimpleScalar LLC, 2003 [2011-01-05]. http://www.simplescalar.com

[18] LiX., AdveS. V., BoseP., RiversA.. Online estimation of architectural vulnerability factor for soft errors [C]. Proceedings of the International Symposium on Computer Architecture, 2008New York, NY, USAACM341-352

[19] DuanL., LiB., PengL.. Versatile prediction and fast estimation of architectural vulnerability factor from processor performance metrics [C]. IEEE 15th Int Symp on High Performance Computer Architecture, 2009Piscataway, NJ, USAIEEE129-140

[20] DesikanR., BurgerD., KecklerS. W., AustinT.Sim-alpha: A validated, execution-driven alpha 21264 simulator [R], 2001Austin, Texas, USADepartment of Computer Science, University of Texas at Austin

[21] SherwoodT., PerelmanE., HamerlyG., CalderB.. Automatically characterizing large scale program behavior [C]. 10th Int Conf on Architectural Support for Programming Languages and Operating Systems, 2002New York, NY, USAACM45-57

[22] ChengY., WangY., XingZ., ZhangM.. Characterizing time-varying behavior and predictability of cache AVF [C]. 2011 Third International Conference on Intelligent Networking and Collaborative Systems, 2011Washington D C, USAIEEE Computer Society720-725

[23] ButtsJ. A., SohiG.. Dynamic dead-instruction detection and elimination [C]. 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002New York, NY, USAACM199-210

[24] FahsB., BoseS., CrumM., SlechtaB., SpadiniF., TungT., PatelS. J., LumettaS. S.. Performance characterization of a hardware mechanism for dynamic optimization [C]. Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001Washington D C, USAIEEE Computer Society16-27

[25] DuesterwaldE., CascavalC., DwarkadasS.. Characterizing and predicting program behavior and its variability [C]. Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, 2003Washington D C, USAIEEE Computer Society220-231

[26] BiswasA., RacunasP., EmerJ., MukherjeeS. S.. Computing accurate AVFs using ACE analysis on performance models: A rebuttal [J]. IEEE Computer Architecture Letters, 2008, 7(1): 21-24