Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

Abstract

The direct current-direct current (DC-DC) converter is designed for 1 T static random access memory (SRAM) used in display driver integrated circuits (ICs), which consists of positive word-line voltage (V_PWL), negative word-line voltage (V_NWL) and half-V_DD voltage (V_HDD) generator. To generate a process voltage temperature (PVT)-insensitive V_PWL and V_NWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a V_PWL regulator and a V_NWL charge pump were proposed for a small-area and low-power design. The proposed V_PWL regulator can provide a large driving current with a small area since it regulates an input voltage (VCI) from 2.5 to 3.3 V. The V_NWL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to V_NWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

Keywords

1 T-static random access memory / direct current-direct current converter / positive word-line voltage / negative word-line voltage / half-V_DD generator

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