Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

Abstract

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm × 100.15 μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

Keywords

eFuse / differential paired efuse cell / one time programmable memory / sensing resistance / D flip-flop based sense amplifier

References

[1] ChaH. K., YunI. H., KimB. J., SoB. C., ChunK. H., NamI. K., LeeK.. A 32-KB standard CMOS antifuse one-time programmable rom embedded in a 16-bit microcontroller [J]. IEEE Journal of Solid-State Circuit, 2006, 41(9): 2115-2124

[2] KulkarniS. H.. High-density 3-D metal-fuse PROM featuring 1.37 μm² 1T1R bit cell in 32nm high-k metal-gate CMOS technology [C]. Symposium on VLSI Circuits, 2009, USA, IEEE Press: 28-29

[3] MATSUFUJI K, NAMEKAWA T, NAKANO H, ITO H, WADA O, OTSUKA N. A 65 nm pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure [C]// Proceedings of IEEE Asian Solid-State Circuit Conference. Jeju: 2007: 212–215.

[4] LiL.-z., KimT. H., ShimO. Y., ParkM. H., HaP. B., KimY. H.. Design of synchronous 256-bit OTP memory [J]. KIMICS of Semiconductors and Communications, 2008, 12(7): 1227-1234

[5] CHOI J S, WEE J K, CHO H Y, KIM P J, OH J K, LEE C H, CHUNG J Y, KIM S C, YANG W. Antifuse EPROM circuit for field programmable DRAM [C]// Proceedings of IEEE International Solid-State Circuits Conference. San Francisco, 2000: 406–407.

[6] BARSATAN R, MAN T Y, CHAN M S. A zero mask one-time programmable memory array for RFID applications [C]// Proceedings of IEEE International Symposium on Circuits and Systems. Island of Kos, 2006: 975–978.

[7] ALAVI M, BOHR M, HICKS J, DENHAM M, CASSENS A, DOUGLAS D, TSAI M C. A PROM element based on silicide agglomeration of poly fuses in a CMOS logic process [C]// Proceedings of IEEE Electron Devices Meeting. Washington, 1997: 855–858.

[8] FELLNER J, BOESMUELLER P, REITER H. Lifetime study for a poly fuse in a 0.35 μm polycide CMOS process [C]// Proceedings of IEEE the 43rd Annual International Reliability Physics Symposium. San Jose, 2005: 446–449.

[9] FELLNER J, PREMSTAETTEN S. A one time programming cell using more than two resistance levels of a polyfuse [C]// Proceedings of IEEE Custom Integrated Circuits Conference. San Jose, 2005: 263–266.

[10] SAFRAN J, LESLIE A, FREDEMAN G, KOTHANDARAMAN C, CESTERO A, CHEN X, RAJEEVAKUMAR R, KIM D K, LI yanzun, MOY D, ROBSON N, KIRIHATA T, IYER S. A compact efuse programmable array memory for SOI CMOS [C]// Proceedings of Symposium on VLSI Circuits. Kyoto, 2007: 72–73.

[11] ElodieE., BrunoA., PhilippeC., PatriceW.. Review of fuse and antifuse solutions for advanced standard CMOS technologies [J]. Microelectronics Journal, 2009, 40(12): 1755-1765

[12] KpthandaramanC., IyerS. K., IyerS. S.. Electrically programmable fuse (efuse) using electromigration in silicides [J]. IEEE Electron Device Letters, 2002, 23(9): 523-525

[13] ROBSON N, SAFRAN J, KOTHANDARAMAN, CESTERO A, CHEN X, RAJEEVAKUMAR, LESLIE A, MOY D, KINHATA T, IYER S. Electrically Programmable Fuse (eFuse): From memory redundancy to autonomic chips [C]// Proceedings of Custom Integrated Circuits Conference. San Jose: IEEE Press, 2007: 799–804.

[14] KimD. H., JangJ. H., JinL. Y., LeeJ. H., HaP. B., KimY. H.. Design and measurement of a 1-kBit eFuse one-time-programmable memory IP based on a BCD process [J]. IEICE Trans Electron, 2010, 93-C(8): 1365-1370

[15] KimJ. H., JangJ. H., JinL. Y., HaP. B., KimY. H.. Design of a low-power OTP memory IP and its measurement [J]. Journal of the Korean Institute of Maritime Information and Communication Sciences, 2010, 14(11): 2541-2547