Effect of grain boundary on electric performance of ZnO nanowire transistor with wrap-around gate

Abstract

A novel grain boundary (GB) model characterized with different angles and positions in the nanowire was set up. By means of device simulator, the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET (Nanowire Field-Effect Transistor) with a wrap-around gate configuration, were explored. With the increase of the grain boundary angle, the electrical performance degrades gradually. When a grain boundary with a smaller angle, such as 5° GB, is located close to the source or drain electrode, the grain boundary is partially depleted by an electric field peak, which leads to the decrease of electron concentration and the degradation of transistor characteristics. When the 90° GB is located at the center of the nanowire, the action of the electric field is balanced out, so the electrical performance of transistor is better than that of the 90° GB located at the other positions.

Keywords

ZnO nanowire / field-effect transistor / grain boundary / electrical performance

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