Performance Analysis and Simulation of BCH(63,56)

ZHAN Yafeng, XIE Dezhun

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Journal of Deep Space Exploration ›› 2017, Vol. 4 ›› Issue (4) : 385-389. DOI: 10.15982/j.issn.2095-7777.2017.04.012

Performance Analysis and Simulation of BCH(63,56)

  • ZHAN Yafeng, XIE Dezhun
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Abstract

BCH(63,56)is widely used in uplink channel of deep space communication for low-complexity implementing,which can check 2 bits error and correct 1 bit error. The performance of BCH(63,56)is studied by theoretical analysis and computer simulation in this paper. On the basis of introducing the basic principle of BCH(63,56),the performance of bits error rate is calculated and the Monte Carlo simulation is carried out. The results show that the coding gain of BCH(63,56)can be up to 2.1 dB when the bit error rate is 1e–5.

Keywords

BCH(63,56) / deep space communication / Monte Carlo simulation

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ZHAN Yafeng, XIE Dezhun. Performance Analysis and Simulation of BCH(63,56). Journal of Deep Space Exploration, 2017, 4(4): 385‒389 https://doi.org/10.15982/j.issn.2095-7777.2017.04.012

References

[1] CCSDS. TC synchronization and channel coding[Z]. [S. l.]:CCSDS,2010.
[2] CCSDS. TC synchronization and channel coding – summary of concept and rationale[Z]. [S. l.]:CCSDS,2006.
[3] Arunkumar S,Kalaivani T. FPGA implementation of CCSDS BCH(63,56)for satellite communication[C]//IEEE International Conference on Electronics Design. [S. l.]:IEEE,2013.
[4] 贺鹤云. LDPC码基础与应用[M]. 北京:人民邮电出版社,2009.
He H Y.Principle and application of LDPC[M].Beijing:Posts & Telecom Press,2009.
[5] 王育民,李晖. 信息论与编码理论[M]. 北京:高等教育出版社,2013.
Wang Y M,Li H. The theory of information and coding[M].Beijing:Higher Education Press,2013.
[6] Lonescu L M,Anton C,Tutanescu I,et al. Hardware implementation of BCH Error-correcting codes on a FPGA[J]. International Journal of Intelligent Computing Research(IJICR),2010,1(3):148-153
[7] Kusumawardani S S,Sutopo B. Designing 1 bit error correcting circuit on FPGA using BCH codes[C]//Proceedings of International Conference on Electrical,Communication,and Information,CECI. [S. l.]:CECI,2001.
[8] 王新梅,肖国镇.纠错码——原理与方法[M]. 西安:西安电子科技大学出版社,2001.
Wang X M,Xiao G Z. Principles and methods of error correcting codes[M].Xi’an: Xidian University Press,2001.
[9] 杨晓琳.循环码理论及其译码算法研究——设计距离为11的二元BCH码构造及其B-M迭代译码算法实现[D].成都:成都理工大学,2008.
Yang X L.Research on cyclic codes and its decoding algorithms—construction of binary BCH codes with design distance 11 and complementation of its B-M iterative decoding algorithm[D].Chengdu: Chengdu University of Technology,2008.
[10] 王永波.BCH译码算法的研究及硬件实现[D].厦门:厦门大学,2011.
Wang Y B.BCH decoding algorithm and hardware implementation[D].Xiamen: Xiamen University,2011.
[11] 江建国.BCH编译码器的设计及验证[D].上海:上海交通大学,2010.
Jiang J G.Design and verification of BCH encoder and decoder[D].Shanghai: Shanghai Jiao Tong University,2010.
[12] 张宗橙.纠错码原理和应用[M].电子工业出版社,2003.
Zhang Z C. Principle and application of error correcting codes[M]. Publishing House of Electronics Industry,2003.
[13] 李志国,张伟功.BCH码迭代译码算法及软件实现方法[J].计算机技术及发展,2007,17(4):171-174.
Li Z G,Zhang W G.Binary BCH code BM decoding Algorithm and soft ware realization[J].Computer Technology and Development, 2007,17(4):171-174.
[14] 王立宁. MATLAB与通信仿真[M]. 人民邮电出版社, 2000.
Wang L N. MATLAB and communication simulation[M].Posts & Telecom Press,2000.
[15] 樊昌信, 曹丽娜. 通信原理[M]. 北京:国防工业出版社, 2012.
Fan C X,Cao L N.Principles of communications[M]. Beijing:National Defense Industry Press,2012.
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