Design and Implementation of Partial Shared Digital Channelized Receiver

Abstract

A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception. Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays (FPGA) resource consumption and parameter estimation accuracy.

Keywords

digital channelized receiver / field programmable gate arrays (FPGA) / non-cooperative / pulse interception