Systolic B ^–1 Circuit in Galois Fields Based on a Quaternary Logic Technique

Abstract

In order to improve the circuit complexity and reduce the long latency of B ^–1 operations, a novel B ^–1 operation in Galois Field GF(2⁴) is presented and the corresponding systolic realization based on multiple-valued logic (MVL) is proposed. The systolic structure employs multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL) to reduce the initial delay and the transistor and wire counts. The performance is evaluated by HSPICE simulation in 0.18 μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature. The initial delay and the sum of transistors and wires in our MVL design are about 43% and 13% lower, respectively, in comparison with other corresponding binary CMOS implementations. The systolic architecture proposed is simple, regular, and modular, well suited for very large scale integration (VLSI) implementations. The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).

Keywords

multiple-valued logic (MVL) / systolic B ^{– 1} circuit / Galois Fields