Universal transfer of full-class metal electrodes for barrier-free two-dimensional semiconductor contacts
Mengyu Hong , Xiankun Zhang , Yu Geng , Yunan Wang , Xiaofu Wei , Li Gao , Huihui Yu , Zhihong Cao , Zheng Zhang , Yue Zhang
InfoMat ›› 2024, Vol. 6 ›› Issue (1) : e12491
Universal transfer of full-class metal electrodes for barrier-free two-dimensional semiconductor contacts
Metal-semiconductor contacts are crucial components in semiconductor devices. Ultrathin two-dimensional transition-metal dichalcogenide semiconductors can sustain transistor scaling for next-generation integrated circuits. However, their performance is often degraded by conventional metal deposition, which results in a high barrier due to chemical disorder and Fermi-level pinning (FLP). Although, transferring electrodes can address these issues, they are limited in achieving universal transfer of full-class metals due to strong adhesion between pre-deposited metals and substrates. Here, we propose a nanobelt-assisted transfer strategy that can avoid the adhesion limitation and enables the universal transfer of over 20 different types of electrodes. Our contacts obey the Schottky-Mott rule and exhibit a FLP of S = 0.99. Both the electron and hole contacts show record-low Schottky barriers of 4.2 and 11.2 meV, respectively. As a demonstration, we construct a doping-free WSe2 inverter with these high-performance contacts, which exhibits a static power consumption of only 58 pW. This strategy provides a universal method of electrode preparation for building high-performance post-Moore electronic devices.
metal electrode transfer / metal-semiconductor contacts / Schottky barrier / two-dimensional semiconductors
| [1] |
|
| [2] |
|
| [3] |
|
| [4] |
|
| [5] |
|
| [6] |
|
| [7] |
|
| [8] |
|
| [9] |
|
| [10] |
|
| [11] |
|
| [12] |
|
| [13] |
|
| [14] |
|
| [15] |
|
| [16] |
|
| [17] |
|
| [18] |
|
| [19] |
|
| [20] |
|
| [21] |
|
| [22] |
|
| [23] |
|
| [24] |
|
| [25] |
|
| [26] |
|
| [27] |
|
| [28] |
|
| [29] |
|
| [30] |
|
| [31] |
|
| [32] |
|
| [33] |
|
| [34] |
|
| [35] |
|
| [36] |
|
| [37] |
|
| [38] |
|
| [39] |
|
| [40] |
|
| [41] |
|
| [42] |
|
| [43] |
|
| [44] |
|
| [45] |
|
| [46] |
|
| [47] |
|
| [48] |
|
| [49] |
|
| [50] |
|
| [51] |
|
| [52] |
|
| [53] |
|
| [54] |
|
| [55] |
|
| [56] |
|
| [57] |
|
| [58] |
|
| [59] |
|
| [60] |
|
| [61] |
|
| [62] |
|
| [63] |
|
| [64] |
|
| [65] |
Semiconductor F. CMOS, the ideal logic family. Nota de aplicación. 1983. |
| [66] |
|
2023 The Authors. InfoMat published by UESTC and John Wiley & Sons Australia, Ltd.
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