Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

Jingjie Niu, Sumin Jeon, Donggyu Kim, Sungpyo Baek, Hyun Ho Yoo, Jie Li, Ji-Sang Park, Yoonmyung Lee, Sungjoo Lee

PDF
InfoMat ›› 2024, Vol. 6 ›› Issue (2) : e12490. DOI: 10.1002/inf2.12490
RESEARCH ARTICLE

Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

Author information +
History +

Abstract

The rapid advancement of AI-enabled applications has resulted in an increasing need for energy-efficient computing hardware. Logic-in-memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual-logic-in-memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectric field-effect transistors (vdW FeFETs). The proposed dual-logic-in-memory device, which also acts as a two-bit storage device, is a single bidirectional polarization-integrated ferroelectric field-effect transistor (BPI-FeFET). It is fabricated by integrating an in-plane vdW ferroelectric semiconductor SnS and an out-of-plane vdW ferroelectric gate dielectric material—CuInP2S6. Four reliable resistance states with excellent endurance and retention characteristics were achieved. The two-bit storage mechanism in a BPI-FeFET was analyzed from two perspectives: carrier density and carrier injection controls, which originated from the out-of-plane polarization of the gate dielectric and in-plane polarization of the semiconductor, respectively. Unlike conventional multilevel FeFETs, the proposed BPI-FeFET does not require additional pre-examination or erasing steps to switch from/to an intermediate polarization, enabling direct switching between the four memory states. To utilize the fabricated BPI-FeFET as a dual-logic-in-memory device, two logical operations were selected (XOR and AND), and their parallel execution was demonstrated. Different types of logic operations could be implemented by selecting different initial states, demonstrating various types of functions required for numerous neural network operations. The flexibility and efficiency of the proposed dual-logic-in-memory device appear promising in the realization of next-generation low-power computing systems.

Keywords

ferroelectric field-effect transistor / in-plane ferroelectricity / logic-in-memory / out-of-plane ferroelectricity

Cite this article

Download citation ▾
Jingjie Niu, Sumin Jeon, Donggyu Kim, Sungpyo Baek, Hyun Ho Yoo, Jie Li, Ji-Sang Park, Yoonmyung Lee, Sungjoo Lee. Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure. InfoMat, 2024, 6(2): e12490 https://doi.org/10.1002/inf2.12490

References

[1]
Ielmini D, Wong HSP. In-memory computing with resistive switching devices. Nat Electron. 2018;1(6):333-343.
[2]
Li MY, Su SK, Wong HSP, Li LJ. How 2D semiconductors could extend Moore's law. Nature. 2019;567(7747):169-170.
[3]
Sebastian A, Le Gallo M, Khaddam-Aljameh R, Eleftheriou E. Memory devices and applications for in-memory computing. Nat Nanotechnol. 2020;15(7):529-544.
[4]
Kim MK, Lee JS. Ferroelectric analog synaptic transistors. Nano Lett. 2019;19(3):2044-2050.
[5]
Mathews S, Ramesh R, Venkatesan T, Benedetto J. Ferroelectric field effect transistor based on epitaxial perovskite heterostructures. Science. 1997;276(5310):238-240.
[6]
Ye HY, Tang YY, Li PF, et al. Metal-free three-dimensional perovskite ferroelectrics. Science. 2018;361(6398):151-155.
[7]
Meyer R, Waser R. Hysteretic resistance concepts in ferroelectric thin films. J Appl Phys. 2006;100(5):051611.
[8]
Müller J, Polakowski P, Mueller S, Mikolajick T. Ferroelectric hafnium oxide based materials and devices: assessment of current status and future prospects. ECS J Solid State Sci and Technol. 2015;4(5):N30-N35.
[9]
Hoffman J, Pan X, Reiner JW, et al. Ferroelectric field effect transistors for memory applications. Adv Mater. 2010;22(26-27):2957-2961.
[10]
Ihlefeld JF, Harris DT, Keech R, Jones JL, Maria JP, Trolier-McKinstry S. Scaling effects in perovskite ferroelectrics: fundamental limits and process-structure-property relations. J Am Ceram Soc. 2016;99(8):2537-2557.
[11]
Zhao Z, Xu K, Ryu H, Zhu W. Strong temperature effect on the ferroelectric properties of CuInP2S6 and its heterostructures. ACS Appl Mater Interfaces. 2020;12(46):51820-51826.
[12]
Belianinov A, He Q, Dziaugys A, et al. CuInP2S6 room temperature layered ferroelectric. Nano Lett. 2015;15(6):3808-3814.
[13]
Susner MA, Belianinov A, Borisevich A, et al. High-Tc layered ferrielectric crystals by coherent spinodal decomposition. ACS Nano. 2015;9(12):12365-12373.
[14]
Fei Z, Zhao W, Palomaki TA, et al. Cobden, ferroelectric switching of a two-dimensional metal. Nature. 2018;560(7718):336-339.
[15]
Higashitarumizu N, Kawamoto H, Lee CJ, et al. Purely in-plane ferroelectricity in monolayer SnS at room temperature. Nat Commun. 2020;11(1):1-9.
[16]
Chang K, Liu J, Lin H, et al. Discovery of robust in-plane ferroelectricity in atomic-thick SnTe. Science. 2016;353(6296):274-278.
[17]
Wang H, Lu W, Hou S, et al. A 2D-SnSe film with ferroelectricity and its bio-realistic synapse application. Nanoscale. 2020;12(42):21913-21922.
[18]
Yan Y, Deng Q, Li S, et al. In-plane ferroelectricity in few-layered GeS and its van der Waals ferroelectric diodes. Nanoscale. 2021;13(38):16122-16130.
[19]
Zheng C, Yu L, Zhu L, et al. Room temperature in-plane ferroelectricity in van der Waals In2Se3. Sci Adv. 2018;4(7):4.
[20]
You L, Liu F, Li H, et al. In-plane ferroelectricity in thin flakes of van der Waals hybrid perovskite. Adv Mater. 2018;30(51):1803249.
[21]
Cui C, Hu WJ, Yan X, et al. Intercorrelated in-plane and out-of-plane ferroelectricity in ultrathin two-dimensional layered semiconductor In2Se3. Nano Lett. 2018;18(2):1253-1258.
[22]
Baek S, Yoo HH, Ju JH, et al. Ferroelectric field-effect-transistor integrated with ferroelectrics heterostructure. Adv Sci. 2020;9(21):2200566.
[23]
Singh P, Baek S, Yoo HH, Niu J, Park JH, Lee S. Two-dimensional CIPS-InSe van der Waals heterostructure ferroelectric field effect transistor for nonvolatile memory applications. ACS Nano. 2022;16(4):5418-5426.
[24]
Si M, Liao PY, Qiu G, Duan Y, Ye PD. Ferroelectric field-effect transistors based on MoS2 and CuInP2S6 two-dimensional van der Waals heterostructure. ACS Nano. 2018;12(7):6700-6705.
[25]
Si M, Saha AK, Gao S, et al. A ferroelectric semiconductor field-effect transistor. Nat Electron. 2019;2(12):580-586.
[26]
Wang X, Zhu C, Deng Y, et al. Van der Waals engineering of ferroelectric heterostructures for long-retention memory. Nat Commun. 2021;12(1):1-8.
[27]
Bao Y, Song P, Liu Y, et al. Gate-tunable in-plane ferroelectricity in few-layer SnS. Nano Lett. 2019;19(8):5109-5117.
[28]
Garcia V, Bibes M. Inside story of ferroelectric memories. Nature. 2012;483(7389):279-280.
[29]
Khosla R, Sharma SK. Integration of ferroelectric materials: an ultimate solution for next-generation computing and storage devices. ACS Appl Electron Mater. 2021;3(7):2862-2897.
[30]
Zeng B, Liu C, Dai S, et al. Electric field gradient-controlled domain switching for size effect-resistant multilevel operations in HfO2-based ferroelectric field-effect transistor. Adv Funct Mater. 2021;31(17):2011077.
[31]
Zhang Q, Xiong H, Wang Q, et al. Tunable multi-bit nonvolatile memory based on ferroelectric field-effect transistors. Adv Electron Mater. 2022;8(5):2101189.
[32]
Xu L, Duan Z, Zhang P, et al. Ferroelectric-modulated MoS2 field-effect transistors as multilevel nonvolatile memory. ACS Appl Mater Interfaces. 2020;12(40):44902-44911.
[33]
Ma C, Tao L, Luo Z, et al. Efficient parallel multi-bit logic-in-memory based on an ultrafast ferroelectric tunnel junction memristor. Adv Electron Mater. 2021;7(3):2000988.
[34]
Wang L, Wang X, Zhang Y, et al. Exploring ferroelectric switching in α-In2Se3 for neuromorphic computing. Adv Funct Mater. 2020;30(45):2004609.
[35]
Xue F, He X, Wang Z, et al. Giant ferroelectric resistance switching controlled by a modulatory terminal for low-power neuromorphic in-memory computing. Adv Mater. 2021; 33(21):2008709.
[36]
Tang B, Tang B, Hussain S, et al. Novel type of synaptic transistors based on a ferroelectric semiconductor channel. ACS Appl Mater Interfaces. 2020;12(22):24920-24928.
[37]
Wang S, Liu L, Gan L, et al. Two-dimensional ferroelectric channel transistors integrating ultra-fast memory and neural computing. Nat Commun. 2021;12(1):1-9.
[38]
Kwon KC, Kwon KC, Zhang Y, et al. In-plane ferroelectric tin monosulfide and its application in a ferroelectric analog synaptic device. ACS Nano. 2020;14(6):7628-7638.
[39]
Borghetti J, Snider GS, Kuekes PJ, Yang JJ, Stewart DR, Williams RS. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature. 2010;464(7290):873-876.
[40]
Liu C, Chen H, Hou X, et al. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat Nanotechnol. 2019;14(7):662-667.
[41]
Hou X, Liu C, Ding Y, Liu L, Wang S, Zhou P. A logic-memory transistor with the integration of visible information sensing-memory-processing. Adv Sci. 2020;7(21):2002072.
[42]
Sun Z, Ambrosi E, Bricalli A, Ielmini D. Logic computing with stateful neural networks of resistive switches. Adv Mater. 2018;30(38):1802554.
[43]
Yin L, Yin L, Cheng R, et al. Two-dimensional unipolar memristors with logic and memory functions. Nano Lett. 2020;20(6):4144-4152.
[44]
Huang W, Wang F, Yin L, et al. Gate-coupling-enabled robust hysteresis for nonvolatile memory and programmable rectifier in van der Waals ferroelectric heterojunctions. Adv Mater. 2020;32(14):1908040.
[45]
Huang K, Zhai M, Liu X, et al. Hf0.5Zr0.5O2 ferroelectric embedded dual-gate MoS2 field effect transistors for memory merged logic applications. IEEE Electron Device Lett. 2020;41(10):1600-1603.
[46]
Liu L, Hou X, Zhang H, Wang J, Zhou P. Ferroelectric field-effect transistors for logic and in-situ memory applications. Nanotechnology. 2020;31(42):424007.
[47]
Luo ZD, Zhang S, Liu Y, et al. Dual-ferroelectric-coupling-engineered two-dimensional transistors for multifunctional in-memory computing. ACS Nano. 2022;16(2):3362-3372.
[48]
Migliato Marega G, Zhao Y, Avsar A, et al. Logic-in-memory based on an atomically thin semiconductor. Nature. 2020;587(7832):72-77.

RIGHTS & PERMISSIONS

2023 2023 The Authors. InfoMat published by UESTC and John Wiley & Sons Australia, Ltd.
PDF

Accesses

Citations

Detail

Sections
Recommended

/