Noise coupling analysis of through-silicon via-based three-dimensional integrated circuits using carbon nanotube interconnects and Teflon dielectric for high-frequency applications

Prathap Reddy Pathakunta Guru , Sravan Abhilash Kothapalli

International Journal of Systematic Innovation ›› 2026, Vol. 10 ›› Issue (3) : 026130034

PDF (7670KB)
International Journal of Systematic Innovation ›› 2026, Vol. 10 ›› Issue (3) :026130034 DOI: 10.6977/IJoSI.202606_10(3).0006
ARTICLE
research-article
Noise coupling analysis of through-silicon via-based three-dimensional integrated circuits using carbon nanotube interconnects and Teflon dielectric for high-frequency applications
Author information +
History +
PDF (7670KB)

Abstract

Conventional two-dimensional integrated circuits are increasingly limited by interconnect delays, power density, and scaling constraints predicted by Moore’s law. Three-dimensional (3D) integrated circuits (ICs), enabled by through-silicon via (TSV) technology, overcome these limitations by vertically stacking dies, thereby reducing interconnect lengths, increasing bandwidth, enhancing functionality, and allowing higher integration density. However, noise coupling in TSV-based 3D ICs significantly impacts signal integrity, especially at high operating frequencies. This study proposes replacing the traditional dielectric silicon dioxide (SiO2) with Teflon due to its lower dielectric constant and higher thermal resistivity. It provides a comprehensive comparative analysis of copper (Cu), carbon nanotube (CNT), and conventional semiconductor core materials using both single-liner and stacked-liner configurations with SiO2 and Teflon dielectrics at 10 GHz and 1 THz. Noise coupling is assessed in terms of electric potential and expressed as attenuation in dB. Results show that CNT interconnects consistently display lower noise coupling than metallic and semiconductor cores. At 10 GHz and 4 µm arc length, Teflon–CNT achieves 10.75 dB compared to 5.03 dB for SiO–Cu. At 1 THz, attenuation decreases to 13.56 dB, representing an 8.53 dB reduction relative to Cu. Although SiO2 remains an industry-standard dielectric, the Teflon-based stacked configuration offers superior high-frequency isolation. Consequently, the CNT–Teflon structure emerges as a promising solution for next-generation high-performance 3D IC systems beyond conventional scaling limits.

Keywords

Teflon / Carbon nanotube / Through-silicon via / Noise coupling / Electrical interference / Three-dimensional integrated circuit

Cite this article

Download citation ▾
Prathap Reddy Pathakunta Guru, Sravan Abhilash Kothapalli. Noise coupling analysis of through-silicon via-based three-dimensional integrated circuits using carbon nanotube interconnects and Teflon dielectric for high-frequency applications. International Journal of Systematic Innovation, 2026, 10 (3) : 026130034 DOI:10.6977/IJoSI.202606_10(3).0006

登录浏览全文

4963

注册一个新账户 忘记密码

References

[1]

Aslani-Amoli, N., ur Rehman, M., Liu, F., Swaminathan, M., Zhuang, C.-G., Zhelev, N. Z., Seok, S.-H., & Kim, C. (2022). Characterization of alumina ribbon ceramic substrates for 5G and mm-wave applications. IEEE Transactions on Components, Packaging and Manufacturing Technology, 12(9), 1432-1445. https://doi.org/10.1109/tcpmt.2022.3196663

[2]

Avouris, P., Chen, Z., & Perebeinos, V. (2007). Carbon-based electronics. Nature Nanotechnology, 2(10), 605-615. https://doi.org/10.1038/nnano.2007.300

[3]

Badugu, D. M., & S, S. (2020). Crosstalk reduction in copper on-chip interconnects with graphene barrier for ternary logic applications. International Journal of Circuit Theory and Applications, 48(12), 2097-2110. https://doi.org/10.1002/cta.2809

[4]

Cadence PCB Solutions . (2018). 3D ICs with TSVs - Design Challenges and Requirements . Cadence Design Systems. Accessed March 20, 2026. Available at: https://resources.pcb.cadence.com/sigrity-whitepapers/3dics-with-tsvs-design-challenges-and-requirements

[5]

Cao, W., Chu, J. H., Parto, K., & Banerjee, K. (2021). A mode-balanced reconfigurable logic gate built in a van der Waals strata. npj 2D Materials and Applications , 5(1), 20. https://doi.org/10.1038/s41699-020-00198-6

[6]

Chandrakar, M., & Majumder, M. K. (2022). Impact of polymer liners on crosstalk induced delay of different TSV shapes. IETE Journal of Research, 70(1), 686-699. https://doi.org/10.1080/03772063.2022.2108915

[7]

Chandrakar, S., Gupta, D., & Majumder, M. K. (2020). Role of through silicon via in 3D integration: Impact on delay and power. Journal of Circuits, Systems and Computers, 30(3), 2150051. https://doi.org/10.1142/S0218126621500511

[8]

Chang, Y. Y., Ko, C. T., Yu, T. H., Hsieh, Y. S., & Chen, K. N. (2015). Modeling and characterization of TSV capacitor and stable low-capacitance implementation for wide-I/O application. IEEE Transactions on Device and Materials Reliability, 15(2), 129-135. https://doi.org/10.1109/TDMR.2015.2397698

[9]

Cho, J., Song, E., Yoon, K., Pak, J. S., Kim, J., Lee, W., Song, T., Kim, K., Lee, J., Lee, H., Park, K., Yang, S., Suh, M., Byun, K., & Kim, J. (2011). Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring. IEEE Transactions on Components, Packaging and Manufacturing Technology, 1(2), 220-233. https://doi.org/10.1109/tcpmt.2010.2101892

[10]

Chou, L.-C., Lee, S.-W., Huang, P.-T., Chang, C.-W., Chiang, C.-H., Wu, S.-L., Chuang, C.-T., Chiou, J.-C., Hwang, W., Wu, C.-H., Chen, K.-H., Chiu, C.-T., Tong, H.-M., & Chen, K.-N. (2014). A TSV-based bio-signal package with μ-probe array. IEEE Electron Device Letters, 35(2), 256-258. https://doi.org/10.1109/led.2013.2293399

[11]

Fang, R., Sun, X., Miao, M., & Jin, Y. (2015). Characteristics of coupling capacitance between signal-ground TSVs considering MOS effect in silicon interposers. IEEE Transactions on Electron Devices, 62(12), 4161-4168. https://doi.org/10.1109/TED.2015.2494538

[12]

Henry, D., Jacquet, F., Neyret, M., Baillin, X., Enot, T., Lapras, V., Brunet-Manquat, C., Charbonnier, J., Aventurier, B., & Sillon, N. (2008). Through silicon vias technology for CMOS image sensors packaging. In 2008 58th Electronic Components and Technology Conference (pp. 556-562). IEEE. https://doi.org/10.1109/ectc.2008.4550028

[13]

Hu, J., Li, D., Liu, M., & Zhu, Z. (2019). A 10-kS/s 625-Hz-bandwidth 65-dB SNDR second-order noise-shaping SAR ADC for biomedical sensor applications. IEEE Sensors Journal, 20(23), 13881-13891. https://doi.org/10.1109/JSEN.2019.2949641

[14]

Hwang, C., Achkir, B., & Fan, J. (2016). Capacitance-enhanced through-silicon via for power distribution networks in 3D ICs. IEEE Electron Device Letters, 37(4), 478-481. https://doi.org/10.1109/LED.2016.2535123

[15]

Koester, S. J., Young, A. M., Yu, R. R., Purushothaman, S., Chen, K.-N., La Tulipe, D. C., Rana, N., Shi, L., Wordeman, M. R., & Sprogis, E. J. (2008). Wafer-level 3D integration technology. IBM Journal of Research and Development, 52(6), 583-597. https://doi.org/10.1147/jrd.2008.5388565

[16]

Kumar, M. S., & Mohanraj, J. (2024a). Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications. International Journal of Electrical & Computer Engineering, 14(3), 2500-2507. https://doi.org/10.11591/ijece.v14i3.pp2500-2507

[17]

Kumar, M. S., & Mohanraj, J. (2024b). Enhancement of liner materials based on nanomaterials to promote sustainability in noise intercourse. International Journal of Informatics and Communication Technology, 13(3), 476-483. https://doi.org/10.11591/ijict.v13i3.pp476-483

[18]

Naeemi, A., & Meindl, J. D. (2007). Conductance modeling for graphene nanoribbon (GNR) interconnects. IEEE Electron Device Letters, 28(5), 428-431. https://doi.org/10.1109/LED.2007.895452

[19]

Pragathi, D., Rakesh, B., Kumar, P. S., Vignesh, N. A., Padma, T., & Panigrahy, A. K. (2020). Noise performance improvement in 3D IC integration utilizing different dielectric materials. Materials Today: Proceedings, 33, 3117-3123. https://doi.org/10.1016/j.matpr.2020.03.737

[20]

Prakash, M. D., Krsihna, B. V., Satyanarayana, B. V. V., Vignesh, N. A., Panigrahy, A. K., & Ahmadsaidulu, S. (2022). A study of an ultrasensitive label free silicon nanowire FET biosensor for cardiac troponin I detection. Silicon, 14(10), 5683-5690. https://doi.org/10.1007/s12633-021-01352-5

[21]

Rafi, V., & Dhal, P. K. (2020). Loss minimization based distributed generator placement at radial distributed system using hybrid optimization technique. In: 2020 International Conference on Computer Communication and Informatics (ICCCI) (pp. 1-6). IEEE. https://doi.org/10.1109/iccci48352.2020.9104145

[22]

Rafi, V., Dhal, P. K., Rajesh, M., Srinivasan, D. R., Chandrashekhar, M., & Reddy, N. M. (2023). Optimal placement of time-varying distributed generators by using crow search and black widow-hybrid optimization. Measurement: Sensors, 30, 100900. https://doi.org/10.1016/j.measen.2023.100900

[23]

Wang, Y., Kim, J. C., Wu, R. J., Martinez, J., Song, X., Yang, J., Zhao, Mkhoyan, Jeong & Chhowalla, M. (2019). Van der Waals contacts between three-dimensional metals and two-dimensional semiconductors. Nature, 568(7750), 70-74. https://doi.org/10.1038/s41586-019-1052-3

[24]

Xu, Y., Zeng, Y., Zhao, Y., Lee, C., He, M., & Liu, Z. (2025). A review of mechanism and technology of hybrid bonding. Journal of Electronic Packaging, 147(1), 010801. https://doi.org/10.1115/1.4065650

[25]

Yasmin, S., Kumar, G. V. N., Rafi, V., Yamuna, P., & Sailaja, K. (2022). Design of bi-directional charger for electric vehicle. In 2022 International Conference on Advances in Computing, Communication and Materials (ICACCM) (pp. 1-6). IEEE. https://doi.org/10.1109/icaccm56405.2022.10009204

[26]

Zheng, J.-C., Zhang, L., Kretinin, A. V., Morozov, S. V., Wang, Y. B., Wang, T., Li, X., Ren, F., Zhang, J., Lu, C.-Y., Chen, J.-C., Lu, M., Wang, H.-Q., Geim, A. K., & Novoselov, K. S. (2016). High thermal conductivity of hexagonal boron nitride laminates. 2D Materials, 3(1), 011004. https://doi.org/10.1088/2053-1583/3/1/011004

PDF (7670KB)

0

Accesses

0

Citation

Detail

Sections
Recommended

/