HyRAS: a hybrid redundancy- and serialization-based fault-tolerant architecture for through-silicon vias

Abstract

Three-dimensional network-on-chips (3D NoCs) are increasingly used to improve scalability in multicore systems. Through-silicon via (TSV) is a critical technology for enabling vertical interconnects between NoC layers. However, TSV-based interlayer connections are highly prone to faults resulting from manufacturing defects, aging, or other sources, which compromise system reliability. To address these challenges, particularly in chiplet-based 3D NoCs, robust fault-tolerant mechanisms are crucial for maintaining operational integrity in the presence of TSV faults. We introduce a novel fault-tolerant architecture designed to ensure persistent communication reliability despite permanent vertical link failures, named HyRAS, a hybrid redundancy- and serialization-based method. Our approach is built on two synergistic mechanisms. First, a lightweight spatial redundancy-based scheme leverages shared TSV resources to mitigate the impact of isolated faults. Second, for more severe fault scenarios, an adaptive serialization-based strategy is employed to maintain connectivity by efficiently using the remaining functional links. The architecture is rigorously evaluated through functional simulations using both synthetic traffic patterns and realistic application workloads. Compared to contemporary fault-tolerant methods, HyRAS achieves up to 28.2% higher throughput under realistic workloads with significant defect clusters. These gains are achieved with only modest overhead, incurring a 14.53% increase in area and 8.87% increase in power consumption relative to the standard redundancy-based router.

Keywords

Three-dimensional network-on-chip (3D NoC) / Through-silicon vias (TSVs) / Redundancy / Fault-tolerant

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The Authors. Published by Zhejiang University Press Co., Ltd.