Parallel VLSI design for the fast 3-D DWT core algorithm

Abstract

By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth, this paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs). Based on the implementation of a 3-D DWT software, a parallel architecture design of a very large-scale integration (VLSI) is produced. It needs three dual-port random-access memory (RAM) to store the temporary results and transpose the matrix, then builds up a pipeline model composed of the three 1-D DWTs. In the design, the finite state machine (FSM) is used well to control the flow. Compared with the serial mode, the experimental results of the post synthesized simulation show that the design method is correct and effective. It can increase the processing speed by about 66%, work at 59 MHz, and meet the real-time needs of the video encoder.

Keywords

3-D DWT, parallel design, transpose the matrix, FSM