Doped low-density parity-check codes

Abstract

In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 ​dB gain compared with the original LDPC code at a frame error rate of 10⁻⁶. Furthermore, the proposed design can lower the error floor of original LDPC codes.

Keywords

LDPC codes / Doped LDPC codes / Tanner graph / Quadratic residue codes / Trapping sets

References

[1] D.J.C. MacKay, R.M. Neal, Near Shannon limit performance of low density parity check codes, Electron, Letture 32 (1996) 1645-1646.

[2] IEEE standard for information technology-local and metropolitan area networks-specific requirements-part 11: wireless LAN Medium Access Control (MAC)and Physical Layer (PHY) specifications amendment 5: enhancements for higher throughput, in: IEEE Std 802.11n- 2009, 2009, pp. 1-565.

[3] IEEE standard for air interface for broadband wireless access systems,in: IEEE Std 802. 16-2017, 2018, pp. 1-2726.

[4] IEEE standard for information technology-telecommunications and information exchange between systems-local and metropolitan area networks-specific requirements part 3: carrier sense multiple access with collision detection (CSMA/ CD) access method and physical layer specifications, in: IEEE Std 802. 3-2008, 2008, pp. 1-2977.

[5] T. Richardson, S. Kudekar, Design of low-density parity check codes for 5G new radio, IEEE Commun. Mag. 56 (3) (2018) 28-34.

[6] C. Di, D. Proietti, E. Telatar, T. Richardson, R. Urbanke, Finite length analysis of low-density parity-check codes on the binary erasure channel, IEEE Trans. Inf. Theor. 48 (6) (2002) 1570-1579.

[7] T. Richardson,Error-floors of LDPC codes, in: Proc. 2003 41th Annual Allerton Conf. Communication, Control, and Computing(Allerton), IEEE, 2003, pp. 1426-1435.

[8] L. Dolecek, Z. Zhang, V. Anantharam, M.J. Wainwright, B. Nikolić, Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes, IEEE Trans. Inf. Theor. 56 (1) (2010) 181-201.

[9] R. Asvadi, A.H. Banihashemi, M. Ahmadian-Attari, Lowering the error floor of LDPC codes using cyclic liftings, IEEE Trans. Inf. Theor. 57 (4) (2011) 2213-2224.

[10] D.V. Nguyen, S.K. Chilappagari, M.W. Marcellin, B. Vasic, On the construction of structured LDPC codes free of small trapping sets, IEEE Trans. Inf. Theor. 58 (4)(2012) 2280-2302.

[11] J. Wang, L. Dolecek, R.D. Wesel, The cycle consistency matrix approach to absorbing sets in separable circulant-based LDPC codes, IEEE Trans. Inf. Theor. 59 (4) (2013) 2293-2314.

[12] X. Tao, Y. Li, Y. Liu, Z. Hu, On the construction of LDPC codes free of small trapping sets by controlling cycles, IEEE Commun. Lett. 22 (1) (2018) 9-12.

[13] A. Sarıduman, A.E. Pusane, Z.C. Taşkın, On the construction of regular QC-LDPC codes with low error floor, IEEE Commun. Lett. 24 (1) (2020) 25-28.

[14] B. Karimi, A.H. Banihashemi, Construction of QC-LDPC codes with low error floor by efficient systematic search and elimination of trapping sets, IEEE Trans. Commun. 68 (2) (2020) 697-712.

[15] M. Lentmaier, K. Zigangirov, On generalized low-density parity-check codes based on Hamming component codes, IEEE Commun. Lett. 3 (8) (1999) 248-250.

[16] G. Liva, W. Ryan, M. Chiani, Quasi-cyclic generalized LDPC codes with low error floors, IEEE Trans. Commun. 56 (1) (2008) 49-57.

[17] Y. Han, W.E. Ryan, Low-floor decoders for LDPC codes, IEEE Trans. Commun. 57 (6) (2009) 1663-1673.

[18] Z. Zhang, L. Dolecek, B. Nikolić, V. Anantharam, M.J. Wainwright, Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices, IEEE Trans. Wireless Commun. 57 (11) (2009) 3258-3268.

[19] A.I.V. Casado, M. Griot, R.D. Wesel, LDPC decoders with informed dynamic scheduling, IEEE Trans. Commun. 58 (12) (2010) 3470-3479.

[20] F. Angarita, J. Valls, V. Almenar, V. Torres, Reduced-Complexity min-sum algorithm for decoding LDPC codes with low error-floor, IEEE Trans. Circuits Syst. I Regul Pap. 61 (7) (2014) 2150-2158.

[21] W. Li, J. Lin, Z. Wang, An efficient post processing scheme to lower the error floor of LDPC decoders, in: Proc. 2017 IEEE International Conference on Communication Technology(ICCT), IEEE, 2017, pp. 122-126.

[22] H.-C. Lee, P.-C. Chou, Y.-L. Ueng, An effective low-complexity error-floor lowering technique for high-rate QC-LDPC codes, IEEE Commun. Lett. 22 (10) (2018) 1988-1991.

[23] Y. Tao, S. Sun, Z. Zhang, Efficient post-processors for improving error-correcting performance of LDPC codes, IEEE Trans. Circuits Syst. I Regul Pap. 66 (10) (2019) 4032-4043.

[24] H. Hatami, D.G.M. Mitchell, D.J. Costello Jr. T. E. Fuja, A threshold-based min-sum algorithm to lower the error floors of quantized LDPC decoders, IEEE Trans. Commun. 68 (4) (2020) 2005-2015.

[25] T. Johansson, K. Zigangirov, A simple one-sweep algorithm for optimal APP symbol decoding of linear block codes, IEEE Trans. Inf. Theor. 44 (7) (1998) 3124-3129.

[26] Y. Li, X. Huang, C. Zhou, Z. Luo, H. Wu, A construction method of doped low-density parity-check codes based on quadratic residue codes, in: Proc. 2021 15th International Symposium on Medical Information and Communication Technology(ISMICT), IEEE, 2021, pp. 221-226.

[27] D. Yuan, L. Li, Y. Liu,Lowering the error floors of low-density parity-check codes with additional check nodes, in: Proc. 2017 IEEE Inf. Theory Workshop(ITW), IEEE, 2017, pp. 146-150.

[28] M. Karimi, A.H. Banihashemi, Efficient algorithm for finding dominant trapping sets of LDPC codes, IEEE Trans. Inf. Theor. 58 (11) (2012) 6942-6958.

[29] C. A. Cole, S. G. Wilson,E. K. Hall, and T. R. Giallorenzi, “A General Method for Finding Low Error Rates of LDPC Codes,” arXiv preprint arXiv:0605051.

[30] O. Milenkovic, E. Soljanin, P. Whiting, Asymptotic spectra of trapping sets in regular and irregular LDPC code ensembles, IEEE Trans. Inf. Theor. 53 (1) (2007) 39-55.

[31] B. Frey, R. Koetter, A. Vardy, Signal-space characterization of iterative decoding, IEEE Trans. Inf. Theor. 47 (2) (2001) 766-781.

[32] X. Zhang, P.H. Siegel, Quantized iterative message passing decoders with low error floor for LDPC codes, IEEE Trans. Commun. 62 (1) (2014) 1-14.

[33] G.A. Margulis, Explicit constructions of graphs without short cycles and low density codes, Combinatorica 2 (1) (1982) 71-78.

[34] ETSI, 5G; NR; multiplexing and channel coding (Release 15), in: 3GPP TS 38.212 V15.2.0, 2018, pp. 1-101.

[35] C. Schlegel, S. Zhang, On the dynamics of the error floor behavior in (regular) LDPC codes, IEEE Trans. Inf. Theor. 56 (7) (2010) 3248-3264.