Physical objects are getting connected to the Internet at an exceptional rate, making the idea of the Internet of Things (IoT) a reality. The IoT ecosystem is evident everywhere in the form of smart homes, health care systems, wearables, connected vehicles, and industries. This has given rise to risks associated with the privacy and security of systems. Security issues and cyber attacks on IoT devices may potentially hinder the growth of IoT products due to deficiencies in the architecture. To counter these issues, we need to implement privacy and security right from the building blocks of IoT. The IoT architecture has evolved over the years, improving the stack of architecture with new solutions such as scalability, management, interoperability, and extensibility. This emphasizes the need to standardize and organize the IoT reference architecture in federation with privacy and security concerns. In this study, we examine and analyze 12 existing IoT reference architectures to identify their shortcomings on the basis of the requirements addressed in the standards. We propose an architecture, the privacy-federated IoT security reference architecture (PF-IoT-SRA), which interprets all the involved privacy metrics and counters major threats and attacks in the IoT communication environment. It is a step toward the standardization of the domain architecture. We effectively validate our proposed reference architecture using the architecture trade-off analysis method (ATAM), an industry-recognized scenario-based approach.
As the hardware industry moves toward using specialized heterogeneous many-core processors to avoid the effects of the power wall, software developers are finding it hard to deal with the complexity of these systems. In this paper, we share our experience of developing a programming model and its supporting compiler and libraries for Matrix-3000, which is designed for next-generation exascale supercomputers but has a complex memory hierarchy and processor organization. To assist its software development, we have developed a software stack from scratch that includes a low-level programming interface and a high-level OpenCL compiler. Our low-level programming model offers native programming support for using the bare-metal accelerators of Matrix-3000, while the high-level model allows programmers to use the OpenCL programming standard. We detail our design choices and highlight the lessons learned from developing system software to enable the programming of bare-metal accelerators. Our programming models have been deployed in the production environment of an exascale prototype system.
Multi-mobile robot systems (MMRSs) are widely used for transportation in industrial scenes such as manufacturing and warehousing. In an MMRS, motion coordination is important as collisions and deadlocks may lead to losses or system stagnation. However, in some scenarios, robot sizes are different when loaded and unloaded, which means that the robots are variable-sized, making motion coordination more difficult. The methods based on zone control need to first divide the environment into disjoint zones, and then allocate the zones statically or dynamically for motion coordination. The zone-control-based methods are not accurate enough for variable-sized multi-mobile robots and reduce the efficiency of the system. This paper describes a motion coordination method based on glued nodes, which can dynamically avoid collisions and deadlocks according to the roadmap structure and the real-time paths of robots. Dynamic features make this method directly applicable to various scenarios, instead of dividing a roadmap into disjoint zones. The proposed method has been applied to many industrial projects, and this study is based on some manufacturing projects for experiments. Theoretical analysis and experimental results show that the proposed algorithm is effective and efficient.
In many robot operation scenarios, the end-effector’s attitude constraints of movement are indispensable for the task process, such as robotic welding, spraying, handling, and stacking. Meanwhile, the inverse kinematics, collision detection, and space search are involved in the path planning procedure under attitude constraints, making it difficult to achieve satisfactory efficiency and effectiveness in practice. To address these problems, we propose a distributed variable density path planning method with attitude constraints (DVDP-AC) for industrial robots. First, a position–attitude constraints reconstruction (PACR) approach is proposed in the inverse kinematic solution. Then, the distributed signed-distance-field (DSDF) model with single-step safety sphere (SSS) is designed to improve the efficiency of collision detection. Based on this, the variable density path search method is adopted in the Cartesian space. Furthermore, a novel forward sequential path simplification (FSPS) approach is proposed to adaptively eliminate redundant path points considering path accessibility. Finally, experimental results verify the performance and effectiveness of the proposed DVDP-AC method under end-effector’s attitude constraints, and its characteristics and advantages are demonstrated by comparison with current mainstream path planning methods.
The main aim of this work is to design a non-fragile sampled data control (NFSDC) scheme for the asymptotic synchronization criteria for interconnected coupled circuit systems (multi-agent systems, MASs). NFSDC is used to conduct synchronization analysis of the considered MASs in the presence of time-varying delays. By constructing suitable Lyapunov functions, sufficient conditions are derived in terms of linear matrix inequalities (LMIs) to ensure synchronization between the MAS leader and follower systems. Finally, two numerical examples are given to show the effectiveness of the proposed control scheme and less conservation of the proposed Lyapunov functions.
An array of two substrate-integrated waveguide (SIW) periodic leaky-wave antennas (LWAs) with sum and difference beam scanning is proposed for application in target detection and tracking. The array is composed of two periodic LWAs with different periods, in which each LWA generates a narrow beam through the n=-1 space harmonic. Due to the two different periods for the two LWAs, two beams with two different directions can be realized, which can be combined into a sum beam when the array is fed in phase or into a difference beam when the array is fed 180° out of phase. The array integrated with 180° hybrid is designed, fabricated, and measured. Measurement results show that the sum beam can reach a gain up to 15.9 dBi and scan from -33.4° to 20.8°. In the scanning range, the direction of the null in the difference beam is consistent with the direction of the sum beam, with the lowest null depth of -40. 8 dB. With the excellent performance, the antenna provides an alternative solution with low complexity and low cost for target detection and tracking.
Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability. In battery-restricted applications such as handheld electronics systems, low-power FPGAs are in great demand. Leakage power almost equals dynamic power in modern integrated circuit technologies, so the reduction of leakage power leads to significant energy savings. We propose a power-efficient architecture for static random access memory (SRAM) based FPGAs, in which two modes (active mode and sleep mode) are defined for each module. In sleep mode, ultra-low leakage power is consumed by the module. The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors. After producing the correct outputs, the module returns to sleep mode. The proposed circuit design reduces the leakage power consumption in both active and sleep modes. The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software. Simulation results show an approximately 95% reduction in leakage power consumption in sleep mode. Moreover, the total power consumption (leakage+dynamic power consumption) is reduced by more than 15% compared with that of the best previous design. The average area overhead (4.26%) is less than those of other power-gating designs.
Carbon nanotube field-effect transistors (CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing (AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input (GDI) technique are merged, and three new AC-based full adders (FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II (NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits’ improvement by about 50% in terms of power-delay-product (PDP) at the cost of area occupation. The Monte Carlo method (MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold (DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit (LSB) parts of more complex arithmetic circuits such as multipliers.