• Journals
  • Articles
  • Figs/Tabs
  • Accesses
RVAM16: A Low-Cost Multiple-ISA Processor Based on RISC-V and ARM Thumb

The increasing demand in the embedded field has led to the emergence of several impressive Instruction Set Architectures (ISAs). However, when processors migrate from one ISA to another, software compatibility issues are unavoidable. Despite the availability of software binary translation systems for ensuring software compatibility, these systems have limitations (e.g. performance and power) in low-cost embedded systems. To solve the problems, a research team led by Professor Libo HUANG published their new research on 18 Mar 2024 in Frontiers of Computer Science co-published by Higher Education Press and Springer Nature.

Targeting two of the most popular ISAs in the embedded field, RISC-V and ARM Thumb, the team proposed RVAM16, a multiple-ISA processor based on hardware binary translation, as a solution to address software compatibility. The multiple-ISA processor not only avoids the startup and additional run time of software DBT systems but also can directly execute all non-native ISA programs, which does not suffer the dilemma of SBT.

By hardware optimization techniques for the ARM Thumb conditional flags, branch instructions, and conditional execution instructions in the RISC-V pipeline, RVAM16 significantly reduces the performance gap between running native ISA programs and non-native ISA programs in HBT-based multiple-ISA processors. Moreover, To keep the area and power consumption of RVAM16 within acceptable limits, the research team designed the 32-bit processor using time-sharing multiplexing the 16-bit data path technology.