Design, fabrication and characterization of dual-channel real space transfer transistor

Abstract

In this paper, using a δ-doping dual-channel structure and GaAs substrate, a real space transfer transistor (RSTT) is designed and fabricated successfully. It has the standard Λ-shaped negative resistance I-V characteristics as well as a level and smooth valley region that the conventional RSTT has. The negative resistance parameters can be varied by changing gate voltage (V_GS). For example, the PVCR varies from 2.1 to 10.6 while V_GS changes from 0.6 V to 1.0 V. The transconductance for I_P (\mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}) is 0.3 mS. The parameters of V_P, V_V and threshold gate voltage (V_T) for negative resistance characteristics arising are all smaller than the value reported in the literature. Therefore, this device is suitable for low dissipation power application.

Keywords

real space transfer transistor (RSTT) / high speed compound three terminal function device / three terminal negative resistance device / hot electron device / electron transfer device

Introduction

The real space transfer transistor (RSTT) [1] is also named negative-resistance field-effect transistor (NERFET) [2], and is also called charge injection transistor (CHINT) [2]. It is a kind of field effect transistor with negative differential resistance (NDR) characteristic in I_DS. The mechanism of this phenomenon is electrons which are accelerated by electric field (V_DS) in the first channel transfer into the second channel; in other words, some current flows out of the first current channel and into the second. Therefore, NDR occurs in the first current channel. Real space is different to momentum space which is usually mentioned in the Gunn effect. The NDR effect is caused by electrons transferring between a high mobility energy valley and the low mobility energy valley in momentum space in the Gunn effect. The real space means the current channel or current layer. The earlier RSTT has dual current channels, the first channel is between source and drain, and the second channel is nearby the substrate under the gate electrode [1].

In recent years, novel RSTTs with dual channels [3] or three channels [4] which are formed by InGaAs/GaAs heterojunction U-shaped quantum well and δ-doping in GaAs V-shaped quantum well were fabricated successfully. There are two characteristics in this novel RSTT.

1) There are two physical mechanisms of NDR in one device: one is electrons transfer between two current channels with different mobility, and the other is shunting effect caused by electrons transfer into the gate electrode.

2) The fabrication processing of the novel RSTT is compatible with high electron mobility transistor (HEMT). The research on RSTT (which was named CHINT in 1996) was first reported in 1996 [5]; however, the RSTT device was not fabricated successfully. In this paper, RSTT with dual channels and GaAs substrate is fabricated successfully, which has Λ-shaped negative I-V characteristics as well as a level and smooth valley region.

The PVCR of this device changes from 2.1 to 10.6 while V_GS varies from 0.6 V to 1.1 V and \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is \mathrm{3}\times {\mathrm{10}}^{-\mathrm{4}}\mathrm{S}. The V_P, V_V, 2 V_GST are smaller than that reported elsewhere, so this device is suitable for application in low power dissipation circuits.

Design and fabrication of dual-channel RSTT

Design of material and device structure of RSTT

Material structure of RSTT

As shown in Fig. 1, the material structure of RSTT is referred to Ref. [3] to compare the results of the two devices. The thickness of the cap layer is 50 nm (d₂=50 nm), because we want to diminish the electrons transfer into the gate electrode when NDR happens. A thick buffer layer is adopted to prevent the influence of impurities and defects.

Device structure of RSTT

As shown in Fig. 1, the distance of source and drain is 5 μm, the dimension of the gate is 1.5 μm × 30 μm, and the distance between gate and source or drain is 1.75 μm.

Fabrication of RSTT

The fabrication process of RSTT is compatible with that of HEMT. The sintering of AuGeNi not only formed an ohmic contact in the source and drain, but also formed two quantum wells (δ-doping well and InGaAs well) connected in parallel by Ge diffusing into InGaAs well. The fabricated RSTT is photographed by optical microscope (zoom in 500×), as shown in Fig. 2.

Measurement of RSTT characteristics

The I-V characteristics of fabricated RSTT are shown in Fig. 3. The parameters of low V_P RSTT (Fig. 3(a)) including V_P (voltage of peak point of I-V characteristic), V_V (voltage of valley point of I-V characteristic) and V_T (voltage of point of I_DS=0 in I-V characteristic) are all smaller than 1.0 V. The parameters of high V_P RSTT (Fig. 3(b)) including V_P and V_V are all bigger than 1.0 V. The extracted RSTT I-V parameters from Fig. 3 are plotted in Figs. 4 and 5, which are the functions of voltage of gate (V_GS).

RSTT with low V_P

From Figs. 3(a) and 4 three conclusions can be drawn.

1) The fabricated device shows the standard Λ-shaped negative resistance I-V characteristics as well as a level and smooth valley region which the conventional RSTT has. The voltage of the gate (V_GS) shows strong modulation to NDR characteristics. The ability of V_GS modulating I_P is token by \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}, \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}=(\mathrm{1}-\mathrm{3})\times {\mathrm{10}}^{-\mathrm{4}}\mathrm{S}. However, \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is not given in Ref. [3].

2) V_P and V_V are not in excess of 1 V under high V_GS, and V_T is not in excess of 0.1 V. They are smaller than Ref. [3] by one order of magnitude.

3) V_P, V_V, I_P, I_V and PVCR increase while V_GS increase in the low V_GS.

RSTT with high V_P

From Figs. 3(b) and 5 two conclusions can be drawn.

1) The shape of high V_P RSTT is similar to that of low V_P RSTT. However, the NDR parameters (i.e., V_P, V_V) of our device and that of Ref. [3] are in one order of magnitude.

2) There are two differences between the low V_P RSTT and high V_P RSTT. The two negative lines are almost vertical, that is, V_V-V_P is very small. Therefore, the two lines of V_P-V_GS and V_V-V_GS are parallel and closed in Fig. 5, PVCR increases first and decreases after that while V_GS increases. The other parameters of NDR (i.e., I_P, I_V, V_P, V_V) increase while V_GS increases.

Discussion

Low V_P and high V_P of RSTT

RSTT with low V_P

From Figs. 3(a) and 4, V_P, V_V, V_T of low V_P RSTT are all smaller than 1 V, and the corresponding currents are all smaller than 50 μA. Therefore, all parameters of low V_P RSTT are smaller than that reported in Ref. [3]. The characteristic of this device is that NDR of I_DS occurs in low V_DS region (refer to Fig. 3(a)). This phenomenon is relevant to the contact between the metal of the gate (Au) and cap layer (GaAs). When the interface is not a typical Schottky contact, the structure similar to the Baritt diode is formed between the gate and GaAs [6]. This structure of gate is called resistive gate [7]. From Ref. [7], when V_GS (positive) is bigger than V_DS of the three-terminal NDR device, and when the hole current from gate to drain is bigger than electron current from source to drain, the I_DS would become negative. From Fig. 6, I_A, I_P and I_V indicate anode current, peak current and valley current, respectively. Meanwhile, V_Z, V_P, V_V and V_BR indicate initial voltage, peak voltage, valley voltage and breakdown voltage. Low V_P RSTT and device from Ref. [7] have the same physical mechanism from the contrast of Figs. 3 and 6.

RSTT with high V_P

From Fig. 3(b), the value of V_P, V_V of high V_P RSTT are both between 1 V to 2 V, and they are obviously bigger than that of low V_P RSTT (shown in Fig. 3(a)). This phenomenon is caused by the ideal Schottky contact between Au and GaAs. Because the ideal Schottky contact induces a high potential barrel, there is a high equivalent resistance in the gate at zero current region. Thus, there is no negative current in the I-V characteristics.

In summary, though the device structure of RSTT is not the same as that in Ref. [7], the physical mechanism can be concluded from the two devices. Thus, we can consider that the reason of low V_P RSTT is resistive gate and that of high V_P RSTT is Schottky gate.

Control ability of V_GS to NDR

From Fig. 3, the modulation ability of the voltage of gate (V_GS) to NDR characteristics of RSTT is strong and obvious. \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}(\approx \mathrm{3.0}\times {\mathrm{10}}^{-\mathrm{4}}\mathrm{S}) indicates the modulation ability of V_GS to I_P. The value of \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}in low and high V_GS region is smaller than that in the middle V_GS region from the experiment. The value of \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is proportional to the number of mutual aligning sub bands of δ-doping V-shaped quantum well and InGaAs/GaAs heterojunction U-shaped quantum well. There is a small number of mutual aligning sub bands in low and high V_GS regions, so the value of \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is small. However, there is a large number of mutual aligning energy sub bands in the middle V_GS region, then the value of \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is big.

RSTT parameters of this work vs Ref. [3]

Table 1 shows the parameters of RSTT in this work and that of Ref. [3]. V_GST indicates the threshold of V_GS which implies the minimal gate voltage occurring NDR in I_DS. From Table 1, we can draw two conclusions.

1) The values of parameters (V_P, I_P, V_GST) of RSTT in this work are smaller than those of the device in Ref. [3]. I_P is 3 orders of magnitude smaller than that in Ref. [3]. There are two reasons that I_P is smaller than that in Ref. [3]. First is that the value of width to length ratio (W/L=30 μm/1.5 μm) of the gate in this work is smaller than that (W/L=100 μm/1.5 μm) in Ref. [3]. The other one is that low V_P RSTT with resistance gate is different from that with Schottky gate in Ref. [3]. In brief, the small values of V_P, I_P and V_GST imply that this RSTT is more suitable for low power dissipation circuits.

2) \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}}(\approx \mathrm{3.0}\times {\mathrm{10}}^{-\mathrm{4}}\mathrm{S} or 0.3 mS) of RSTT can be obtained from this work; however, it cannot be obtained from Ref. [3].

Analyses of NDR mechanism of RSTT

There are two NDR physical mechanisms of dual-channel RSTT which has been referred to at the beginning of this paper. The two mechanisms include:

a) Electron transfer from InGaAs/GaAs heterojunction U-shaped channel to δ-doping V-shaped channel.

b) Electron transfer from δ-doping V-shaped channel to gate electrode.

The author of this paper considers that a) is a major mechanism of RSTT in this paper. There are two main reasons as follows:

1) There is little chance that electrons transfer from δ-doping V-shaped channel to gate electrode, because the thickness of the cap layer is 50 nm (d₂ = 50 nm).

2) From Ref. [3] we can conclude that PVCR of RSTT whose NDR mechanism is a) equals to the value of electron mobility of InGaAs ratio to that of δ-doping GaAs, namely, {\mu }_{\mathrm{I}\mathrm{n}\mathrm{G}\mathrm{a}\mathrm{A}\mathrm{s}}/{\mu }_{\mathrm{\delta }}=12000\mathrm{c}{\mathrm{m}}^2\cdot {(\mathrm{V}\cdot \mathrm{S})}^{-\mathrm{1}}/17\mathrm{00}\mathrm{c}{\mathrm{m}}^2\cdot {(\mathrm{V}\cdot \mathrm{S})}^{-\mathrm{1}}\approx \mathrm{8}. The PVCR of RSTT in this work is 7-10 and the biggest value is 11 from Table 1. Therefore, we conclude that a) is the main NDR mechanism of RSTT in this paper.

Conclusions

The dual-channel RSTT with GaAs substrate has been designed and fabricated successfully. The studied device has the standard Λ-shaped negative resistance I-V characteristics as well as a level and smooth valley region that the conventional RSTT has. When V_GS is in 0.6-1.0 V, PVCR changes from 2.1 to 10.6. The maximum of \mathrm{\Delta }{I}_{\mathrm{P}}/\mathrm{\Delta }{V}_{\mathrm{G}\mathrm{S}} is 0.3 mS. The parameters of NDR including V_P, V_V, V_T and V_GST are all smaller than that reported before. Therefore, this device is suitable for low power dissipation circuits. Under the elementary analysis of RSTT in this work, we can conclude that the main NDR mechanism of RSTT is electrons transfer from the InGaAs/GaAs heterojunction U-shaped quantum well into the δ-doping V-shaped quantum well.

As we have seen, RSTT is one of three-terminal NDR functional devices. It is applied in controllable micro- and milli-wave oscillator, as well as in logic elements or storage circuits which are used in high speed integrated logic circuits. The device structure of dual-channel RSTT is similar to HEMT, so it can be integrated in HEMT circuits monolithically. The I-V characteristics of RSTT is similar to that of resonant tunneling transistor (RTT) formed by resonant tunneling diode (RTD) and HEMT connected in series, so it can be used instead of RTD+ HEMT in circuits application.

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