School of Microelectronics, Xidian University, Xi’an 710071, China
szluan@mail.xidian.edu.cn
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Published
2009-03-05
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2009-03-05
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Abstract
A two-dimensional (2D) model for the subthreshold current in the dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET with a single halo is presented. The model considers single halo doping in the channel near the source and a dual-material gate to derive the channel potential using the explicit solution of the 2D Poisson’s equation. Together with the conventional drift-diffusion theory, this results in the development of a subthreshold current model for the novel structure. Model verification is carried out using the 2D device simulator ISE. Excellent agreement is obtained between the calculations and the simulated results of the model.
Suzhen LUAN, Hongxia LIU, Renxu JIA, Jin WANG.
Two-dimensional subthreshold current model for dual-material gate SOI nMOSFETs with single halo.
Front. Electr. Electron. Eng., 2009, 4(1): 98-103 DOI:10.1007/s11460-009-0008-z
To keep pace with progress in process technology, CMOS devices have been scaled down, continuously pushing the MOS technology into the nanometer era. However, with the reduction of channel length, some effects such as short-channel effects (SCEs), drain-induced barrier lowering (DIBL) and hot carrier effect (HCE) are becoming increasingly important, since they degrade controllability of the gate voltage over a drain current because of increased charge-sharing from the drain/source regions. Dual-material gate (DMG) silicon-on-insulator (SOI) MOSFETs in Refs. [1–4] seem to be a very promising option for ultimate scaling of CMOS technology because of their excellent SCE suppression and high carrier transport efficiency. However, DMG SOI MOSFETs show considerable DIBL in the sub-100 nm regime. Boron pocket implantation has been reported to effectively improve MOSFET performance in Refs. [5–7]. In the past years, the reverse SCEs (RSCEs) of boron pocket-implanted MOSFETs have been extensively studied from an experimental or analytical approach. Single-halo MOSFET structures have been introduced for bulk substrates in Ref. [8] as well as SOI MOSFETs in Ref. [9] to adjust threshold voltage. Most of them focus on the threshold voltage behavior and driving capability in Ref. [10–12]. With the device scaling down and the integration increasing, power consumption seems to be the challenge of very-large-scale integration (VLSI) devices. Therefore, the characteristics in the subthreshold region limit the development of devices.
In this article, the structure of a DMG SOI MOSFET with a single halo (DMGH) is investigated and a subthreshold potential for the novel device is developed. Based on an explicit solution to the channel potential, the subthreshold current can be modeled using the drift-diffusion equation. The model development of subthreshold current is described in detail. Model verification is carried out and presented using the results from 2D device simulator ISE.
Modeling description
2D surface potential
A cross-sectional view of a fully depleted DMG SOI MOSFET with a single halo (DMGH) is shown in Fig. 1(a). For comparison, the conventional DMG SOI MOSFET is shown in Fig. 1(b). The doping concentration NA near the source region is higher than NB elsewhere in the channel. Neglecting the influence of fixed oxide charges on the electrostatics of the channel, the potential distribution in the silicon film before the onset of strong inversion can be written as
where is the dielectric constant of silicon film, tSi is the film thickness, L is the device channel length, and Ni is the channel doping concentration, N1=NA,N2=N3=NB.
The potential profile in the vertical direction, i.e., the y-dependence of фi(x,y), can be approximated by a simple parabolic function as proposed by Young in Ref. [3] for fully depleted SOI MOSFETs:
whereфSi(x) is the surface potential and the arbitrary coefficients ci1(x) and ci2(x) are just functions of x.
Considering the gate and doping profile, the channel can be divided into three zones. Therefore, the flat band voltage for the three zones would be different, which are given as
where are the metal work functions and the silicon work functions, respectively.
The semiconductor work function can be written as
where is the Fermi potential, Eg is the silicon bandgap, is the electron affinity, Vt is the thermal voltage, and ni is the intrinsic carrier concentration.
The Poisson’s equation is solved separately using the following boundary conditions:
1) Electric flux at the gate/front-oxide interface and the buried oxide/back channel interface is continuous for the three zones:
where ϵox is the dielectric constant of the oxide; tf, tb are the gate oxide and buried oxide thickness respectively; , where Vgs is the gate-to-source voltage; is the potential function along the back oxide-silicon interface; , where Vbs is the substrate bias;VFB,fi,VFB,bi,i=1,2,3 are the front- and back-channel flat band voltages, respectively.
2) The surface potential and electric flux at the interface of the three zones are continuous and shown as follows:
3) The potentials at the source and drain end are as follows:
where is the built-in potential across the body-source junction.
The constants in Eq. (2) can be derived from the above boundary conditions. Substituting Eq. (2) into Eq. (1), we can obtain
Here, where
The above equations are simple second-order differential equations with constant coefficients, and thus the expression for the surface potential is of the form:
where
By using boundary conditions (5) –(7) to solve the constants in Eq. (8), the constants are
where
2D subthreshold current model
Based on the drift-diffusion equation, the electron current density Jn in an nMOSFET can be written as
where n(x) is the electron density along the channel, and Dn is the electron diffusion coefficient, which can be related to the thermal voltage Vt and electron mobility μn through the Einstein relation as Dn=Vtμn.
By multiplying Eq. (10) by an integrating factor of exp(-фSi(x)/Vt), the right side of the equation can be transformed into an exact derivative. Considering the boundary condition (7) and different doping concentrations in the channel, the current density can be expressed as
The drain current Ids in the channel is obtained by integrating the current density over the cross section of the conducting channel, which yields
where W is the device channel width and Seff is the effective channel thickness, which can be estimated as the distance from the surface to the position when the electrostatic potential has changed by Vt. According to the Gauss’ law, the vertical component of the electric field at the surface Vt /Seff, is equal to Qdep/ϵSi (Qdep is the depletion charge) in the subthreshold region. Thus,
where is the surface potential at the onset of strong inversion.
In the structure of a DMGH SOI MOSFET, since the channel is divided into three parts, the subthreshold current in the channel can be solved iteratively. According to Eq. (9), a complicated process is needed to calculate the denominator in Eq. (11). To come up with an analytical solution for Eq. (11), we propose to approximate фSi(x) as a piecewise linear function in the channel. From this, фSi(x) in Eq. (9) can be unified and rewritten as
Thus, the denominator in Eq. (11) is reduced to
where фS,m isфS(x) at x=mΔx, Δx=xm-xm-1=L/N .
Applying this analytical method to Eq. (12), the subthreshold current density can be calculated.
Results and discussion
To verify the proposed analytical model, the 2D device simulator ISE was used to evaluate the results from the present model. For DMGH, typical values of the work function for gate metals M1 and M2 are chosen as 4.77 and 4.10 eV, respectively. The doping concentration close to the source is NA=4×1017 cm-3, the rest in the channel is NB=1×1017 cm-3, and the drain and source doping concentration is ND=1×1020 cm-3. The thicknesses of the front oxide, silicon film and buried oxide are 2, 12 and 200 nm respectively. The work function of the buried gate is equal to that of M1. The electron mobility in the channel μn is assumed as 500 cm2/(V·s).
The position-dependent potentials in the channel calculated from the present model are illustrated in Fig. 2 for DMGH SOI with two different channel lengths (L=50 and 100 nm) and various drain biases. It is seen from Fig. 2 that a potential step profile exists near the interface of different gates. Because of step potential, when beyond 0.1 V drain bias, the additional drain voltage increase is not absorbed under the M1 but under the M2. In other words, the M1 region is screened from the drain potential variations. Consequently,Vds has a very small influence on M1, even for the 50 nm channel length. The novel structure can suppress the SCEs as a result of the screening effect. Moreover, an extra potential step exists near the halo boundary besides the one near the interface between the two gates, which further suppresses the DIBL.
Figure 3 shows the subthreshold current characteristics of DMGH SOI NMOSFETs for different channel lengths and various drain voltages respectively. The symbols represent the calculation results using the exact channel potential; the dotted lines denote the calculated results using the piecewise-approximated channel potential. It is found that the analytical and exact results agree very well with each other, thus validating the analytical approach. Note that the subthreshold current increases with the reduced channel length, i.e., the shorter the channel length, the larger the subthreshold current at a given gate voltage will be. For a given gate bias, the subthreshold current differences with various drain biases increase with decreasing channel length because of a more significant DIBL effect in a shorter channel MOS device. For comparison, the subthreshold current for the conventional DMG SOI MOSFET is also given. It is found that the introduction of a single halo can significantly degrade the off-state current. Since the analytical approach with Eq. (15) is valid, it is used in the following discussions.
It is shown in Fig. 4 that subthreshold current-voltage characteristics with various work function differences between two gate materials. In Fig. 4, the symbols and solid lines represent the model calculations using the piecewise-approximated channel potentials and simulated results from 2D device simulator ISE. A very good agreement is found between the model predictions and simulated results. With the work function difference increasing, the subthreshold current decreases rapidly.
The subthreshold current-voltage curves for three different halo dopings are illustrated in Fig. 5. It can be seen that the subthreshold current is reduced with increasing halo implant doping. A very good agreement is found between the model prediction using the piecewise-approximated channel potentials and simulated results from ISE for the sub-threshold region; beyond this region, however, the model is not valid and a large discrepancy between the model and simulations is observed.
Figure 6 shows the variation of subthreshold characteristics with the effective halo lateral length L1 as shown in Fig. 1, with the lengths L and L, kept constant. It can be seen from the figure that the subthreshold currents change monotonically with halo lengths, and that the longer the halo length is, the smaller the current at a given gate voltage will be. It can be seen from Fig. 7 that with the length of M1 (‘control gate’) increasing, at the fixed channel length L3, the threshold currents decrease. This happens because the threshold voltage is enhanced with the L2 increase.
Conclusions
An analytical subthreshold potential model for DMG SOI MOSFETs with a single halo is developed. Based on the potential profile, the subthreshold current model is derived with the conventional drift-diffusion theory. To simplify the calculation process for subthreshold current, an analytical method with piecewise-approximated channel potentials is proposed. An excellent agreement is found between the model predictions using both exact and piecewise-approximated channel potentials. The present model is useful for evaluating the subthreshold current for a novel MOS technology. Again, a good agreement is obtained between the model prediction results and simulated results from 2-dimensional device simulator ISE.
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Higher Education Press and Springer-Verlag Berlin Heidelberg
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