Research on switching throughput of traffic manager in core routers

Abstract

A general model is made to analyze switching throughput of traffic manager in core routers. By designing a real traffic manager that uses the OC-48c interface, the whole system is analyzed and it is pointed out that at least four HSSLs should be employed per CSIX interface when using Vitesse s GigaStream switch chipset. Meanwhile, at the CSIX interface, the CFrame should be constructed according to the actual size of the last cell of each IP packet. The above principles can guarantee forwarding of IP packets at line rate. A general relationship between throughput and buffering scheme of IP packets in the external memory is given, which is useful in the design of switch fabric in core routers.