Internet of Things (IoT) devices are becoming increasingly ubiquitous, and their adoption is growing at an exponential rate. However, they are vulnerable to security breaches, and traditional security mechanisms are not enough to protect them. The massive amounts of data generated by IoT devices can be easily manipulated or stolen, posing significant privacy concerns. This paper is to provide a comprehensive overview of the integration of blockchain and IoT technologies and their potential to enhance the security and privacy of IoT systems. The paper examines various security issues and vulnerabilities in IoT and explores how blockchain-based solutions can be used to address them. It provides insights into the various security issues and vulnerabilities in IoT and explores how blockchain can be used to enhance security and privacy. The paper also discusses the potential applications of blockchain-based IoT (B-IoT) systems in various sectors, such as healthcare, transportation, and supply chain management. The paper reveals that the integration of blockchain and IoT has the potential to enhance the security, privacy, and trustworthiness of IoT systems. The multi-layered architecture of B-IoT, consisting of perception, network, data processing, and application layers, provides a comprehensive framework for the integration of blockchain and IoT technologies. The study identifies various security solutions for B-IoT, including smart contracts, decentralized control, immutable data storage, identity and access management (IAM), and consensus mechanisms. The study also discusses the challenges and future research directions in the field of B-IoT.
As the number of cores in a multicore system increases, the communication pressure on the interconnection network also increases. The network-on-chip (NoC) architecture is expected to take on the ever-expanding communication demands triggered by the ever-increasing number of cores. The communication behavior of the NoC architecture exhibits significant spatial–temporal variation, posing a considerable challenge for NoC reconfiguration. In this paper, we propose a traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing to adapt to the varying traffic flows with a high flexibility. First, a modified input port is introduced to support buffer sharing between adjacent ports. Specifically, the modified input port can be dynamically reconfigured to react to on-demand traffic. Second, it is ascertained that a centralized output-oriented buffer management works well with the reconfigurable input ports. Finally, this reconfiguration method can be implemented with a low overhead hardware design without imposing a great burden on the system implementation. The experimental results show that compared to other proposals, the proposed NoC architecture can greatly reduce the packet latency and improve the saturation throughput, without incurring significant area and power overhead.
Dynamic bandwidth allocation (DBA) is a fundamental challenge in the realm of networking. The rapid, accurate, and fair allocation of bandwidth is crucial for network service providers to fulfill service-level agreements, alleviate link congestion, and devise strategies to counter network attacks. However, existing bandwidth allocation algorithms operate mainly on the control plane of the software-defined networking paradigm, which can lead to considerable probing overhead and convergence latency. Moreover, contemporary network architectures necessitate a hierarchical bandwidth allocation system that addresses latency requirements. We introduce a finegrained, hierarchical, and scalable DBA algorithm, i.e., the HSDBA algorithm, implemented on the programmable data plane. This algorithm reduces network overhead and latency between the data plane and the controller, and it is proficient in dynamically adding and removing network configurations. We investigate the practicality of HSDBA using protocol-oblivious forwarding switches. Experimental results show that HSDBA achieves fair bandwidth allocation and isolation guarantee within approximately 25 packets. It boasts a convergence speed 0.5 times higher than that of the most recent algorithm, namely, approximate hierarchical allocation of bandwidth (AHAB); meanwhile, it maintains a bandwidth enforcement accuracy of 98.1%.
Joint Photographic Experts Group (JPEG) format is extensively used for images in many practical applications due to its excellent compression ratio and satisfactory image quality. Considering compelling concerns about the invasion of privacy, this paper proposes an effective reversible data hiding scheme for encrypted JPEG bitstreams, to provide security and privacy for both secret messages and valuable carriers. First, a format-compatibility and file size preserving encryption algorithm is applied to encipher the plaintext JPEG image into a noise-like version. Then, we present an effective reversible data hiding scheme in encrypted JPEG bitstreams using adaptive RZL rotation, where the secret messages are concealed with the sequence of RZL pairs. When the authorized user receives the marked encrypted JPEG bitstreams, the error-free extraction of secret messages and the lossless recovery of the original plaintext JPEG image can be accomplished separately. Extensive experiments are conducted to show that, compared to some state-of-the-art schemes, the proposed scheme has a superior performance in terms of embedding capacity, while keeping file size preservation and format compatibility.
This paper uses the semi-tensor product (STP) of matrices and adopts algebraic methods to study the controllability, reachability, and stabilizability of extended finite state machines (EFSMs). First, we construct the bilinear dynamic system model of the EFSM, laying the foundation for further research. Second, combined with this bilinear dynamic system model, we propose theorems for the controllability, reachability, and stabilizability of the bilinear dynamic system model of the EFSM. Finally, we design an algorithm to determine the controllability and stabilizability of the EFSM. The correctness of the main results is verified through examples.
This paper focuses on addressing the problems of finite-time boundedness and guaranteed cost control in switched systems under asynchronous switching. To reduce redundant information transmission and alleviate data congestion of sensor nodes, two schemes are proposed: the event-triggered scheme (ETS) and the round-robin protocol (RRP). These schemes are designed to ensure that the system exhibits good dynamic characteristics while reducing communication resources. In the field of finite-time control, a switching signal is designed using the admissible edge-dependent average dwell time (AED-ADT) method. This method involves a slow AED-ADT switching and a fast AED-ADT switching, which are respectively suitable for finite-time stable and finite-time unstable situations of the controlled system within the asynchronous switching interval. By constructing a double-mode dependent Lyapunov function, the finite-time bounded criterion and the controller gain of the switched systems are obtained. Finally, the validity of the proposed results is showcased by implementing a buck-boost voltage circuit model.
The performance of complementary metal oxide semiconductor (CMOS) circuits is affected by electromagnetic interference (EMI), and the study of the circuit’s ability to resist EMI will facilitate the design of circuits with better performance. Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process; their EMI resistance performance deserves further study. This paper introduces three kinds of NOT gate circuits: conventional voltage-mode CMOS, MOS current-mode logic (MCML) with voltage signal of input and output, and current-mode CMOS with current signal of input and output. The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation, and a disturbance level factor is defined to compare the effects of different interference terminals, interference signals’ waveforms, and interference signals’ frequencies on the circuits in the 65 nm process. The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits. Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies, and the higher the operating frequency of the current-mode CMOS circuits, the better the resistance performance of the circuits to EMI. Additionally, the effects of different temperatures and different processes on the resistance performance of three circuits are also studied. In the temperature range of −40 ℃ to 125 ℃, the higher the temperature, the weaker the resistance ability of voltage-mode CMOS and MCML circuits, and the stronger the resistance ability of current-mode CMOS circuits. In the 28 nm process, the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits. The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process, while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process. This study provides a basis for the design of current-mode CMOS circuits against EMI.
At the Annual International Cryptology Conference in 2019, Gohr introduced a deep learning based cryptanalysis technique applicable to the reduced-round lightweight block ciphers with a short block of SPECK32/64. One significant challenge left unstudied by Gohr’s work is the implementation of key recovery attacks on large-state block ciphers based on deep learning. The purpose of this paper is to present an improved deep learning based framework for recovering keys for large-state block ciphers. First, we propose a key bit sensitivity test (KBST) based on deep learning to divide the key space objectively. Second, we propose a new method for constructing neural distinguisher combinations to improve a deep learning based key recovery framework for large-state block ciphers and demonstrate its rationality and effectiveness from the perspective of cryptanalysis. Under the improved key recovery framework, we train an efficient neural distinguisher combination for each large-state member of SIMON and SPECK and finally carry out a practical key recovery attack on the large-state members of SIMON and SPECK. Furthermore, we propose that the 13-round SIMON64 attack is the most effective approach for practical key recovery to date. Noteworthly, this is the first attempt to propose deep learning based practical key recovery attacks on 18-round SIMON128, 19-round SIMON128, 14-round SIMON96, and 14-round SIMON64. Additionally, we enhance the outcomes of the practical key recovery attack on SPECK large-state members, which amplifies the success rate of the key recovery attack in comparison to existing results.