A BCH error correction scheme applied to FPGA with embedded memory

Yang LIU; Jie LI; Han WANG; Debiao ZHANG; Kaiqiang FENG; Jinqiang LI

doi:10.1631/FITEE.2000323

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Front. Inform. Technol. Electron. Eng ›› 2021, Vol. 22 ›› Issue (8) : 1127-1139. DOI: 10.1631/FITEE.2000323

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A BCH error correction scheme applied to FPGA with embedded memory

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Abstract

Given the potential for bit flipping of data on a memory medium, a high-speed parallel Bose–Chaudhuri–Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

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Error correction algorithm / Bose–Chaudhuri–Hocquenghem (BCH) code / Field programmable gate array (FPGA) / NAND flash

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Yang LIU, Jie LI, Han WANG, Debiao ZHANG, Kaiqiang FENG, Jinqiang LI. A BCH error correction scheme applied to FPGA with embedded memory. Front. Inform. Technol. Electron. Eng, 2021, 22(8): 1127‒1139 https://doi.org/10.1631/FITEE.2000323