Function synthesis algorithm based on RTD-based three-variable universal logic gates

Mao-qun YAO, Kai YANG, Ji-zhong SHEN, Cong-yuan XU

PDF(483 KB)
PDF(483 KB)
Front. Inform. Technol. Electron. Eng ›› 2017, Vol. 18 ›› Issue (10) : 1654-1664. DOI: 10.1631/FITEE.1601730
Article
Article

Function synthesis algorithm based on RTD-based three-variable universal logic gates

Author information +
History +

Abstract

Compared with complementary metal–oxide semiconductor (CMOS), the resonant tunneling device (RTD) has better performances; it is the most promising candidate for next-generation integrated circuit devices. The universal logic gate is an important unit circuit because of its powerful logic function, but there are few function synthesis algorithms that can implement an n-variable logical function by RTD-based universal logic gates. In this paper, we propose a new concept, i.e., the truth value matrix. With it a novel disjunctive decomposition algorithm can be used to decompose an arbitrary n-variable logical function into three-variable subset functions. On this basis, a novel function synthesis algorithm is proposed, which can implement arbitrary n-variable logical functions by RTD-based universal threshold logic gates (UTLGs), RTD-based three-variable XOR gates (XOR3s), and RTD-based three-variable universal logic gate (ULG3s). When this proposed function synthesis algorithm is used to implement an n-variable logical function, if the function is a directly disjunctive decomposition one, the circuit structure will be very simple, and if the function is a non-directly disjunctive decomposition one, the circuit structure will be simpler than when using only UTLGs or ULG3s. The proposed function synthesis algorithm is straightforward to program, and with this algorithm it is convenient to implement an arbitrary n-variable logical function by RTD-based universal logic gates.

Keywords

Resonant tunneling device (RTD) / Disjunctive decomposition algorithm / Universal logic gate / Truth value matrix / Function synthesis algorithm

Cite this article

Download citation ▾
Mao-qun YAO, Kai YANG, Ji-zhong SHEN, Cong-yuan XU. Function synthesis algorithm based on RTD-based three-variable universal logic gates. Front. Inform. Technol. Electron. Eng, 2017, 18(10): 1654‒1664 https://doi.org/10.1631/FITEE.1601730

References

[1]
Altun , M., Riedel , M.D., 2012. Logic synthesis for switching lattices. IEEE Trans. Comput., 61(11):1588–1600. https://doi.org/10.1109/TC.2011.170
[2]
Beiu , V., Quintana , J.M., Avedillo , M.J., 2003. VLSI imple-mentations of threshold logic—a comprehensive survey. IEEE Trans. Neur. Networks, 14(5):1217–1243. https://doi.org/10.1109/TNN.2003.816365
[3]
Bertacco , V., Damiani , M., 1997. The disjunctive decomposi-tion of logic functions. IEEE/ACM Int. Conf. on Computer-Aided Design, p.78–82. https://doi.org/10.1109/ICCAD.1997.643371
[4]
Czajkowski , T.S., Brown , S.D., 2008. Functionally linear decomposition and synthesis of logic circuits for FPGAs. Comput.-Aided Des. Integr. Circ. Syst., 27(12):2236–2249. https://doi.org/10.1109/TCAD.2008.2006144
[5]
Falkowski , B.J.,Kannurao , S., 2001. Analysis of disjoint decomposition of balanced Boolean functions through the Walsh spectrum. Comput. Dig. Techn., 148(2):71–78. https://doi.org/10.1049/ip-cdt:20010205
[6]
Fan , D.L., Sharad , M., Roy , K., 2014. Design and synthesis of ultralow energy spin-memristor threshold logic. IEEE Trans. Nanotechnol., 13(3):574–583. https://doi.org/10.1109/TNANO.2014.2312177
[7]
Files , C.M.,Perkowski , M.A., 2000. New multivalued func-tional decomposition algorithms based on MDDs. Comput.-Aided Des. Integr. Circ. Syst., 19(9):1081–1086. https://doi.org/10.1109/43.863648
[8]
Hrynkiewicz , E., Kolodzinski , S., 2010. An Ashenhurst dis-joint and non-disjoint decomposition of logic functions in Reed-Muller spectral domain. Proc. 17th Int. Conf. on Mixed Design of Integrated Circuits and Systems, p.200–204.
[9]
Iwai , H., 2013. Future of nano CMOS technology. Proc. Symp. on Microelectronics Technology and Devices, p.1–10.
[10]
Kolodzinski , S., Hrynkiewicz , E., 2009. An utilisation of Boolean differential calculus in variables partition cal-culation for decomposition of logic functions. 12th Int. Symp. on Design and Diagnostics of Electronic Circuits & Systems, p.34–37. https://doi.org/10.1109/DDECS.2009.5012095
[11]
Likharev , K.K., 2008. Hybrid CMOS/nanoelectronic circuits: opportunities and challenges. J. Nanoelectron. Opto- electron., 3(3):203–230. https://doi.org/10.1166/JNO.2008.301
[12]
Liu , M.C., Lin , D.D., Pei , D.Y., 2011. Fast algebraic attacks and decomposition of symmetric Boolean functions. IEEE Trans. Inform. Theory, 57(7):4817–4821. https://doi.org/10.1109/TIT.2011.2145690
[13]
Mazumder , P., Kulkarni , S., Bhattacharya , M., 1998. Digital circuit applications of resonant tunneling devices. Proc. IEEE, 86(4):664–686. https://doi.org/10.1109/5.663544
[14]
Mirhoseini , S.M., Sharifi , M.J., Bahrepour , D., 2010. New RTD-based general threshold gate topologies and appli-cation to three-input XOR logic gates. J. Electr. Comput. Eng., 35(1):1–4. https://doi.org/10.1155/2010/463925
[15]
Muramatsu , N., Okazaki , H., Waho , T., 2005. A novel oscil-lation circuit using a resonate-tunneling diode. IEEE Int. Symp. on Circuits and Systems, p.2341–2344. https://doi.org/10.1109/ISCAS.2005.1465094
[16]
Ngwira , S.M., Tshabalala , P., 2002. Neural network analysis for the identification of optimal variable orderings in the decomposition of complex logic functions. Comput. Dig. Techn., 149(5):240–244. https://doi.org/10.1049/ip-cdt:20020405
[17]
Nikodem , M., 2013. Synthesis of multithreshold threshold gates based on negative differential resistance devices. IET Circ. Dev. Syst., 7(5):232-242. https://doi.org/10.1049/iet-cds.2012.0368
[18]
Wei , Y.,Shen , J.Z., 2011. Novel universal threshold logic gate based on RTD and its application. Microelectron. J., 42: 851–854. https://doi.org/10.1016/j.mejo.2011.04.005
[19]
Yao , M.Q., Yang , K., Xu , C.Y., , 2015. Design of a novel RTD-based three-variable universal logic gate. Front. Inform. Technol. Electron. Eng., 16(8):694–699. https://doi.org/10.1631/FITEE.1500102
[20]
Zhang , R., Gupta , P., Zhong , L., 2005. Threshold network synthesis and optimization and its application to nano-technologies. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 24(1):107–118. https://doi.org/10.1109/TCAD.2004.839468
[21]
Zheng , Y.X., Huang , C., 2009. Complete logic functionality of reconfigurable RTD circuit elements. IEEE Trans. Nano- technol., 8(5):631–642. https://doi.org/10.1109/TNANO.2009.2016563

RIGHTS & PERMISSIONS

2017 Zhejiang University and Springer-Verlag GmbH Germany
PDF(483 KB)

Accesses

Citations

Detail

Sections
Recommended

/